[PATCH] D129765: [DAG] SimplifyDemandedBits - don't early-out for multiple use values (WIP)

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

The code still looks OK as far as I can see. Slightly different order but still doing the same thing. Subreg liveness can be pretty nice for dealing with the nested register classes under MVE, it would be a shame to loose it.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D129765/new/

https://reviews.llvm.org/D129765