[PATCH] D129735: [WIP][RISCV] Add new pass to transform undef to zero-init for vector values.

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng updated this revision to Diff 444645.
kito-cheng added a comment.

It filter out most unnecessary zero-init but still several code gen degradation.

Changes:

- Only zero init vector value if the user is early-clobber instruction or INSERT_REG.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129735/new/

https://reviews.llvm.org/D129735

Files:
  llvm/lib/Target/RISCV/CMakeLists.txt
  llvm/lib/Target/RISCV/RISCV.h
  llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/O3-pipeline.ll
  llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
  llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-fptrunc-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-trunc-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp-mask.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp-mask.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
  llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
  llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
  llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
  llvm/test/CodeGen/RISCV/rvv/vfptosi-vp-mask.ll
  llvm/test/CodeGen/RISCV/rvv/vfptoui-vp-mask.ll
  llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vtrunc-vp-mask.ll
  llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll

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