[PATCH] D129765: [DAG] SimplifyDemandedBits - don't early-out for multiple use values (WIP)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: foad, dmgreen, craig.topper, spatel, lenary.
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SimplifyDemandedBits currently early-outs for multi-use values beyond the root node for simplification (just returning the knownbits), which is missing a number of optimizations as there are plenty of cases where we can still simplify when initially demanding all elements/bits.

I'm still yak shaving a few of the outstanding regressions but I'd appreciate some advice on 2 test cases:

@foad @dmgreen  I currently have an assertion in mve-sext-masked-load.ll when '-early-live-intervals' is set - @foad added this to the test last year - can you remember why? I can also make the assert go away if I disable ARMSubtarget::enableSubRegLiveness() for MVE integer ops - @dmgreen have you any suggestions on what might be wrong? I don't have much experience with MVE instructions.

@lenary Any thoughts on what is going so wrong in aea-erratum-fix.ll? SimplifyDemandedBits does tend to mess with specific patterns that this might be depending on.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D129765

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
  llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
  llvm/test/CodeGen/AArch64/parity.ll
  llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
  llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
  llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
  llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
  llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
  llvm/test/CodeGen/AMDGPU/udiv64.ll
  llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
  llvm/test/CodeGen/ARM/aes-erratum-fix.ll
  llvm/test/CodeGen/RISCV/rv32zbp.ll
  llvm/test/CodeGen/Thumb2/mve-laneinterleaving-cost.ll
  llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
  llvm/test/CodeGen/Thumb2/mve-sext-masked-load.ll
  llvm/test/CodeGen/Thumb2/mve-vabdus.ll
  llvm/test/CodeGen/Thumb2/mve-vmull-splat.ll
  llvm/test/CodeGen/Thumb2/mve-vst3.ll
  llvm/test/CodeGen/X86/combine-bitreverse.ll
  llvm/test/CodeGen/X86/fshl-splat-undef.ll
  llvm/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
  llvm/test/CodeGen/X86/illegal-bitfield-loadstore.ll
  llvm/test/CodeGen/X86/sad.ll
  llvm/test/CodeGen/X86/smul_fix_sat_constants.ll
  llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
  llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll

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