[PATCH] D127982: [X86][FP16] Enable vector support for FP16 emulation

Phoebe Wang via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Jul 14 03:20:06 PDT 2022


pengfei added inline comments.


================
Comment at: llvm/lib/Target/X86/X86InstrSSE.td:571
             (VMOVUPSYmr addr:$dst, VR256:$src)>;
-  def : Pat<(store (v16i16 VR256:$src), addr:$dst),
             (VMOVUPSYmr addr:$dst, VR256:$src)>;
----------------
skan wrote:
> Why did you move the pattern down?
No idea. Should be accident :)


================
Comment at: llvm/lib/Target/X86/X86InstrSSE.td:635
 
+let Predicates = [HasSSE2] in {
+  def : Pat<(alignedloadv8f16 addr:$src),
----------------
skan wrote:
> Should we use `UseSSE2` here?
I think AVX instruction is always preferred, but yes, `UseSSE2` can make sure of that.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D127982/new/

https://reviews.llvm.org/D127982



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