[llvm] 055b409 - [AArch64][NFC] Drop 'V' from ASIMD FP convert, other, D/Q-form regex

[Cullen Rhodes via llvm-commits]

Author: Cullen Rhodes
Date: 2022-07-14T09:32:20Z
New Revision: 055b409cea9f0672595e6a17446cb4d770f10bc8

URL: https://github.com/llvm/llvm-project/commit/055b409cea9f0672595e6a17446cb4d770f10bc8
DIFF: https://github.com/llvm/llvm-project/commit/055b409cea9f0672595e6a17446cb4d770f10bc8.diff

LOG: [AArch64][NFC] Drop 'V' from ASIMD FP convert, other, D/Q-form regex

In the Cortex A57 Optimization Guide [1] VCVTAU (AArch32) is incorrectly
listed in the AArch64 instructions for instruction groups:

  - ASIMD FP convert, other, D-form
  - ASIMD FP convert, other, Q-form

It's meant to be FCVTAU, this will be fixed in future releases of the guide.

[1] https://developer.arm.com/documentation/uan0015/b

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64SchedA57.td

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64SchedA57.td b/llvm/lib/Target/AArch64/AArch64SchedA57.td
index 6ede9495dba2..8ce229374000 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA57.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA57.td
@@ -460,9 +460,9 @@ def : InstRW<[A57Write_5cyc_2V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCM
 // ASIMD FP convert, long and narrow
 def : InstRW<[A57Write_8cyc_3V], (instregex "^FCVT(L|N|XN)v")>;
 // ASIMD FP convert, other, D-form
-def : InstRW<[A57Write_5cyc_1V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i64)")>;
+def : InstRW<[A57Write_5cyc_1V], (instregex "^[FSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i64)")>;
 // ASIMD FP convert, other, Q-form
-def : InstRW<[A57Write_5cyc_2V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v4f32|v2f64|v4i32|v2i64)")>;
+def : InstRW<[A57Write_5cyc_2V], (instregex "^[FSU]CVT([AMNPZ][SU])?(_Int)?(v4f32|v2f64|v4i32|v2i64)")>;
 
 // ASIMD FP divide, D-form, F32
 def : InstRW<[A57Write_17cyc_1W], (instregex "FDIVv2f32")>;