[PATCH] D129735: [WIP][RISCV] Add new pass to transform undef to zero-init for vector values.

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp:117
+      .addImm(/* VLMAX */ -1)
+      .addImm(4);
+
----------------
The filed is SEW, but seems like I don't have good way to figure out right SEW setting without tracing UD chain, and sometime we even don't have that info, but fix that to 16 or 32 can work correctly, but sub-optimal.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129735/new/

https://reviews.llvm.org/D129735