[PATCH] D129646: [RISCV] Disable subregister liveness by default

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added a comment.

Personally I would prefer keep sub register liveness enabled by default, that indeed improved code gen quality especially when program contain segment load/store.

As I can see the most root cause is the undef and poison value in the program, ideally that should not appeared in program IMO, so I would prefer to trade some code gen quality about undef/poison value to make sub register liveness still enabled, and buy more time to model the constraint issue right.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D129646/new/

https://reviews.llvm.org/D129646