[PATCH] D129735: [RISCV] Add new pass to transform undef to zero-init for vector values.

[Kito Cheng via Phabricator via llvm-commits]

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RISC-V vector instruction has register overlapping constraint for certain
instructions, and will cause illegal instruction trap if violated, we use
early clobber to model this constraint, but it can't prevent register allocator
allocated same or overlapped if the input register is undef value, so convert
IMPLICIT_DEF to zero initialized could prevent that happen, it's not best way
to resolve this, and it might emit redundant zero initialized instruction for
undef value, so ideally we should model the constraint right, but before we
model the constraint right, it's the only way to prevent that happen.

See also: https://github.com/llvm/llvm-project/issues/50157


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D129735

Files:
  llvm/lib/Target/RISCV/CMakeLists.txt
  llvm/lib/Target/RISCV/RISCV.h
  llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

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