[PATCH] D129727: [ARM64EC 11/?] Add support for lowering variadic indirect calls.

[chenglin.bi via Phabricator via llvm-commits]

bcl5980 added inline comments.


================
Comment at: llvm/test/CodeGen/AArch64/arm64ec-cfg.ll:363-365
+; CHECK-NEXT:    mov x8, sp
+; CHECK-NEXT:    sub x0, x8, x15, lsl #4
+; CHECK-NEXT:    mov sp, x0
----------------
It looks Microsoft generate code：

```
sub         sp,sp,x15,lsl #4
```
Does anyone know why we can't accept SP as input/ouput for the instruction?

```
def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),
          (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;
```





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  https://reviews.llvm.org/D129727/new/

https://reviews.llvm.org/D129727