[llvm] e32864b - [RISCV] Add test case show missed opportunity to turn slliw+sraiw into slli+srai.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-07-13T12:55:12-07:00
New Revision: e32864b60568316a5fc967086380f44076cd818b

URL: https://github.com/llvm/llvm-project/commit/e32864b60568316a5fc967086380f44076cd818b
DIFF: https://github.com/llvm/llvm-project/commit/e32864b60568316a5fc967086380f44076cd818b.diff

LOG: [RISCV] Add test case show missed opportunity to turn slliw+sraiw into slli+srai.

slliw and sraiw have no compressed encodings. slli and srai
do have compressed encodings.

Pre-commit for D129688

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll b/llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll
index ab6e1127b907..6d0a59980f01 100644
--- a/llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll
+++ b/llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll
@@ -158,3 +158,16 @@ define i64 @test11(i32* %0, i64 %1) {
   %5 = ashr exact i64 %4, 32
   ret i64 %5
 }
+
+; TODO: We should use slli+srai to enable the possibility of compressed
+; instructions.
+define i32 @test12(i32 signext %0) {
+; RV64I-LABEL: test12:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slliw a0, a0, 17
+; RV64I-NEXT:    sraiw a0, a0, 15
+; RV64I-NEXT:    ret
+  %2 = shl i32 %0, 17
+  %3 = ashr i32 %2, 15
+  ret i32 %3
+}