[llvm] 2ce0a5c - [RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
Alex Bradbury via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 13 11:37:52 PDT 2022
Author: Alex Bradbury
Date: 2022-07-13T19:37:34+01:00
New Revision: 2ce0a5c8c383f2514c4fb10858d0e8607d5f21b4
URL: https://github.com/llvm/llvm-project/commit/2ce0a5c8c383f2514c4fb10858d0e8607d5f21b4
DIFF: https://github.com/llvm/llvm-project/commit/2ce0a5c8c383f2514c4fb10858d0e8607d5f21b4.diff
LOG: [RISCV][test][NFC] Regenerate RISC-V tests with update_llc_test_checks.py -u
If a change alters more than a couple of tests it's really handy to be
able to regenerate any that were created by update_llc_test_checks.py
with something like `update_llc_test_checks.py -u
llvm/test/CodeGen/RISCV`. I noticed this causes some extraneous changes
(perhaps due to hand editing). This commit addresses that by updating
any fails that are modified by update_llc_test_checks.py -u.
Added:
Modified:
llvm/test/CodeGen/RISCV/double-arith.ll
llvm/test/CodeGen/RISCV/double-fcmp.ll
llvm/test/CodeGen/RISCV/float-arith.ll
llvm/test/CodeGen/RISCV/half-arith.ll
llvm/test/CodeGen/RISCV/half-fcmp.ll
llvm/test/CodeGen/RISCV/rv32zknd-intrinsic.ll
llvm/test/CodeGen/RISCV/rv32zkne-intrinsic.ll
llvm/test/CodeGen/RISCV/rv32zknh-intrinsic.ll
llvm/test/CodeGen/RISCV/rv64zknd-intrinsic.ll
llvm/test/CodeGen/RISCV/rv64zknd-zkne-intrinsic.ll
llvm/test/CodeGen/RISCV/rv64zkne-intrinsic.ll
llvm/test/CodeGen/RISCV/rv64zknh-intrinsic.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/double-arith.ll b/llvm/test/CodeGen/RISCV/double-arith.ll
index dc3228586d6d1..f7c4b48b72155 100644
--- a/llvm/test/CodeGen/RISCV/double-arith.ll
+++ b/llvm/test/CodeGen/RISCV/double-arith.ll
@@ -660,17 +660,11 @@ define double @fnmadd_d_2(double %a, double %b, double %c) nounwind {
}
define double @fnmadd_d_3(double %a, double %b, double %c) nounwind {
-; RV32IFD-LABEL: fnmadd_d_3:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fmadd.d ft0, fa0, fa1, fa2
-; RV32IFD-NEXT: fneg.d fa0, ft0
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fnmadd_d_3:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fmadd.d ft0, fa0, fa1, fa2
-; RV64IFD-NEXT: fneg.d fa0, ft0
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fnmadd_d_3:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fmadd.d ft0, fa0, fa1, fa2
+; CHECKIFD-NEXT: fneg.d fa0, ft0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fnmadd_d_3:
; RV32I: # %bb.0:
@@ -701,15 +695,10 @@ define double @fnmadd_d_3(double %a, double %b, double %c) nounwind {
define double @fnmadd_nsz(double %a, double %b, double %c) nounwind {
-; RV32IFD-LABEL: fnmadd_nsz:
-; RV32IFD: # %bb.0:
-; RV32IFD-NEXT: fnmadd.d fa0, fa0, fa1, fa2
-; RV32IFD-NEXT: ret
-;
-; RV64IFD-LABEL: fnmadd_nsz:
-; RV64IFD: # %bb.0:
-; RV64IFD-NEXT: fnmadd.d fa0, fa0, fa1, fa2
-; RV64IFD-NEXT: ret
+; CHECKIFD-LABEL: fnmadd_nsz:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fnmadd.d fa0, fa0, fa1, fa2
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fnmadd_nsz:
; RV32I: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/double-fcmp.ll b/llvm/test/CodeGen/RISCV/double-fcmp.ll
index 146265953b7b5..9f59dd21106a0 100644
--- a/llvm/test/CodeGen/RISCV/double-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/double-fcmp.ll
@@ -9,10 +9,10 @@
; RUN: | FileCheck -check-prefix=RV64I %s
define i32 @fcmp_false(double %a, double %b) nounwind {
-;CHECKIFD-LABEL: fcmp_false:
-;CHECKIFD: # %bb.0:
-;CHECKIFD-NEXT: li a0, 0
-;CHECKIFD-NEXT: ret
+; CHECKIFD-LABEL: fcmp_false:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: li a0, 0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_false:
; RV32I: # %bb.0:
@@ -29,10 +29,10 @@ define i32 @fcmp_false(double %a, double %b) nounwind {
}
define i32 @fcmp_oeq(double %a, double %b) nounwind {
-;CHECKIFD-LABEL: fcmp_oeq:
-;CHECKIFD: # %bb.0:
-;CHECKIFD-NEXT: feq.d a0, fa0, fa1
-;CHECKIFD-NEXT: ret
+; CHECKIFD-LABEL: fcmp_oeq:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: feq.d a0, fa0, fa1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_oeq:
; RV32I: # %bb.0:
@@ -59,10 +59,10 @@ define i32 @fcmp_oeq(double %a, double %b) nounwind {
}
define i32 @fcmp_ogt(double %a, double %b) nounwind {
-;CHECKIFD-LABEL: fcmp_ogt:
-;CHECKIFD: # %bb.0:
-;CHECKIFD-NEXT: flt.d a0, fa1, fa0
-;CHECKIFD-NEXT: ret
+; CHECKIFD-LABEL: fcmp_ogt:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: flt.d a0, fa1, fa0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_ogt:
; RV32I: # %bb.0:
@@ -89,10 +89,10 @@ define i32 @fcmp_ogt(double %a, double %b) nounwind {
}
define i32 @fcmp_oge(double %a, double %b) nounwind {
-;CHECKIFD-LABEL: fcmp_oge:
-;CHECKIFD: # %bb.0:
-;CHECKIFD-NEXT: fle.d a0, fa1, fa0
-;CHECKIFD-NEXT: ret
+; CHECKIFD-LABEL: fcmp_oge:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fle.d a0, fa1, fa0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_oge:
; RV32I: # %bb.0:
@@ -121,10 +121,10 @@ define i32 @fcmp_oge(double %a, double %b) nounwind {
}
define i32 @fcmp_olt(double %a, double %b) nounwind {
-;CHECKIFD-LABEL: fcmp_olt:
-;CHECKIFD: # %bb.0:
-;CHECKIFD-NEXT: flt.d a0, fa0, fa1
-;CHECKIFD-NEXT: ret
+; CHECKIFD-LABEL: fcmp_olt:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: flt.d a0, fa0, fa1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_olt:
; RV32I: # %bb.0:
@@ -151,10 +151,10 @@ define i32 @fcmp_olt(double %a, double %b) nounwind {
}
define i32 @fcmp_ole(double %a, double %b) nounwind {
-;CHECKIFD-LABEL: fcmp_ole:
-;CHECKIFD: # %bb.0:
-;CHECKIFD-NEXT: fle.d a0, fa0, fa1
-;CHECKIFD-NEXT: ret
+; CHECKIFD-LABEL: fcmp_ole:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fle.d a0, fa0, fa1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_ole:
; RV32I: # %bb.0:
@@ -181,12 +181,12 @@ define i32 @fcmp_ole(double %a, double %b) nounwind {
}
define i32 @fcmp_one(double %a, double %b) nounwind {
-;CHECKIFD-LABEL: fcmp_one:
-;CHECKIFD: # %bb.0:
-;CHECKIFD-NEXT: flt.d a0, fa0, fa1
-;CHECKIFD-NEXT: flt.d a1, fa1, fa0
-;CHECKIFD-NEXT: or a0, a1, a0
-;CHECKIFD-NEXT: ret
+; CHECKIFD-LABEL: fcmp_one:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: flt.d a0, fa0, fa1
+; CHECKIFD-NEXT: flt.d a1, fa1, fa0
+; CHECKIFD-NEXT: or a0, a1, a0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_one:
; RV32I: # %bb.0:
@@ -247,12 +247,12 @@ define i32 @fcmp_one(double %a, double %b) nounwind {
}
define i32 @fcmp_ord(double %a, double %b) nounwind {
-;CHECKIFD-LABEL: fcmp_ord:
-;CHECKIFD: # %bb.0:
-;CHECKIFD-NEXT: feq.d a0, fa1, fa1
-;CHECKIFD-NEXT: feq.d a1, fa0, fa0
-;CHECKIFD-NEXT: and a0, a1, a0
-;CHECKIFD-NEXT: ret
+; CHECKIFD-LABEL: fcmp_ord:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: feq.d a0, fa1, fa1
+; CHECKIFD-NEXT: feq.d a1, fa0, fa0
+; CHECKIFD-NEXT: and a0, a1, a0
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_ord:
; RV32I: # %bb.0:
@@ -279,13 +279,13 @@ define i32 @fcmp_ord(double %a, double %b) nounwind {
}
define i32 @fcmp_ueq(double %a, double %b) nounwind {
-;CHECKIFD-LABEL: fcmp_ueq:
-;CHECKIFD: # %bb.0:
-;CHECKIFD-NEXT: flt.d a0, fa0, fa1
-;CHECKIFD-NEXT: flt.d a1, fa1, fa0
-;CHECKIFD-NEXT: or a0, a1, a0
-;CHECKIFD-NEXT: xori a0, a0, 1
-;CHECKIFD-NEXT: ret
+; CHECKIFD-LABEL: fcmp_ueq:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: flt.d a0, fa0, fa1
+; CHECKIFD-NEXT: flt.d a1, fa1, fa0
+; CHECKIFD-NEXT: or a0, a1, a0
+; CHECKIFD-NEXT: xori a0, a0, 1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_ueq:
; RV32I: # %bb.0:
@@ -346,11 +346,11 @@ define i32 @fcmp_ueq(double %a, double %b) nounwind {
}
define i32 @fcmp_ugt(double %a, double %b) nounwind {
-;CHECKIFD-LABEL: fcmp_ugt:
-;CHECKIFD: # %bb.0:
-;CHECKIFD-NEXT: fle.d a0, fa0, fa1
-;CHECKIFD-NEXT: xori a0, a0, 1
-;CHECKIFD-NEXT: ret
+; CHECKIFD-LABEL: fcmp_ugt:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fle.d a0, fa0, fa1
+; CHECKIFD-NEXT: xori a0, a0, 1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_ugt:
; RV32I: # %bb.0:
@@ -377,11 +377,11 @@ define i32 @fcmp_ugt(double %a, double %b) nounwind {
}
define i32 @fcmp_uge(double %a, double %b) nounwind {
-;CHECKIFD-LABEL: fcmp_uge:
-;CHECKIFD: # %bb.0:
-;CHECKIFD-NEXT: flt.d a0, fa0, fa1
-;CHECKIFD-NEXT: xori a0, a0, 1
-;CHECKIFD-NEXT: ret
+; CHECKIFD-LABEL: fcmp_uge:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: flt.d a0, fa0, fa1
+; CHECKIFD-NEXT: xori a0, a0, 1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_uge:
; RV32I: # %bb.0:
@@ -410,11 +410,11 @@ define i32 @fcmp_uge(double %a, double %b) nounwind {
}
define i32 @fcmp_ult(double %a, double %b) nounwind {
-;CHECKIFD-LABEL: fcmp_ult:
-;CHECKIFD: # %bb.0:
-;CHECKIFD-NEXT: fle.d a0, fa1, fa0
-;CHECKIFD-NEXT: xori a0, a0, 1
-;CHECKIFD-NEXT: ret
+; CHECKIFD-LABEL: fcmp_ult:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: fle.d a0, fa1, fa0
+; CHECKIFD-NEXT: xori a0, a0, 1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_ult:
; RV32I: # %bb.0:
@@ -441,11 +441,11 @@ define i32 @fcmp_ult(double %a, double %b) nounwind {
}
define i32 @fcmp_ule(double %a, double %b) nounwind {
-;CHECKIFD-LABEL: fcmp_ule:
-;CHECKIFD: # %bb.0:
-;CHECKIFD-NEXT: flt.d a0, fa1, fa0
-;CHECKIFD-NEXT: xori a0, a0, 1
-;CHECKIFD-NEXT: ret
+; CHECKIFD-LABEL: fcmp_ule:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: flt.d a0, fa1, fa0
+; CHECKIFD-NEXT: xori a0, a0, 1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_ule:
; RV32I: # %bb.0:
@@ -472,11 +472,11 @@ define i32 @fcmp_ule(double %a, double %b) nounwind {
}
define i32 @fcmp_une(double %a, double %b) nounwind {
-;CHECKIFD-LABEL: fcmp_une:
-;CHECKIFD: # %bb.0:
-;CHECKIFD-NEXT: feq.d a0, fa0, fa1
-;CHECKIFD-NEXT: xori a0, a0, 1
-;CHECKIFD-NEXT: ret
+; CHECKIFD-LABEL: fcmp_une:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: feq.d a0, fa0, fa1
+; CHECKIFD-NEXT: xori a0, a0, 1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_une:
; RV32I: # %bb.0:
@@ -503,13 +503,13 @@ define i32 @fcmp_une(double %a, double %b) nounwind {
}
define i32 @fcmp_uno(double %a, double %b) nounwind {
-;CHECKIFD-LABEL: fcmp_uno:
-;CHECKIFD: # %bb.0:
-;CHECKIFD-NEXT: feq.d a0, fa1, fa1
-;CHECKIFD-NEXT: feq.d a1, fa0, fa0
-;CHECKIFD-NEXT: and a0, a1, a0
-;CHECKIFD-NEXT: xori a0, a0, 1
-;CHECKIFD-NEXT: ret
+; CHECKIFD-LABEL: fcmp_uno:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: feq.d a0, fa1, fa1
+; CHECKIFD-NEXT: feq.d a1, fa0, fa0
+; CHECKIFD-NEXT: and a0, a1, a0
+; CHECKIFD-NEXT: xori a0, a0, 1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_uno:
; RV32I: # %bb.0:
@@ -536,10 +536,10 @@ define i32 @fcmp_uno(double %a, double %b) nounwind {
}
define i32 @fcmp_true(double %a, double %b) nounwind {
-;CHECKIFD-LABEL: fcmp_true:
-;CHECKIFD: # %bb.0:
-;CHECKIFD-NEXT: li a0, 1
-;CHECKIFD-NEXT: ret
+; CHECKIFD-LABEL: fcmp_true:
+; CHECKIFD: # %bb.0:
+; CHECKIFD-NEXT: li a0, 1
+; CHECKIFD-NEXT: ret
;
; RV32I-LABEL: fcmp_true:
; RV32I: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/float-arith.ll b/llvm/test/CodeGen/RISCV/float-arith.ll
index 66f60c0288ab3..9fb3de2f0d002 100644
--- a/llvm/test/CodeGen/RISCV/float-arith.ll
+++ b/llvm/test/CodeGen/RISCV/float-arith.ll
@@ -611,6 +611,12 @@ define float @fnmadd_s_3(float %a, float %b, float %c) nounwind {
; RV64IF-NEXT: fneg.s fa0, ft0
; RV64IF-NEXT: ret
;
+; CHECKIF-LABEL: fnmadd_s_3:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fmadd.s ft0, fa0, fa1, fa2
+; CHECKIF-NEXT: fneg.s fa0, ft0
+; CHECKIF-NEXT: ret
+;
; RV32I-LABEL: fnmadd_s_3:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
@@ -648,6 +654,11 @@ define float @fnmadd_nsz(float %a, float %b, float %c) nounwind {
; RV64IF-NEXT: fnmadd.s fa0, fa0, fa1, fa2
; RV64IF-NEXT: ret
;
+; CHECKIF-LABEL: fnmadd_nsz:
+; CHECKIF: # %bb.0:
+; CHECKIF-NEXT: fnmadd.s fa0, fa0, fa1, fa2
+; CHECKIF-NEXT: ret
+;
; RV32I-LABEL: fnmadd_nsz:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
diff --git a/llvm/test/CodeGen/RISCV/half-arith.ll b/llvm/test/CodeGen/RISCV/half-arith.ll
index b221e075aac9d..39cea9c2c65e9 100644
--- a/llvm/test/CodeGen/RISCV/half-arith.ll
+++ b/llvm/test/CodeGen/RISCV/half-arith.ll
@@ -14,10 +14,10 @@
; instructions that don't directly match a RISC-V instruction.
define half @fadd_s(half %a, half %b) nounwind {
-;CHECKIZFH-LABEL: fadd_s:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: fadd.h fa0, fa0, fa1
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fadd_s:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fadd.h fa0, fa0, fa1
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fadd_s:
; RV32I: # %bb.0:
@@ -75,10 +75,10 @@ define half @fadd_s(half %a, half %b) nounwind {
}
define half @fsub_s(half %a, half %b) nounwind {
-;CHECKIZFH-LABEL: fsub_s:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: fsub.h fa0, fa0, fa1
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fsub_s:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fsub.h fa0, fa0, fa1
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fsub_s:
; RV32I: # %bb.0:
@@ -136,10 +136,10 @@ define half @fsub_s(half %a, half %b) nounwind {
}
define half @fmul_s(half %a, half %b) nounwind {
-;CHECKIZFH-LABEL: fmul_s:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: fmul.h fa0, fa0, fa1
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fmul_s:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fmul.h fa0, fa0, fa1
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fmul_s:
; RV32I: # %bb.0:
@@ -197,10 +197,10 @@ define half @fmul_s(half %a, half %b) nounwind {
}
define half @fdiv_s(half %a, half %b) nounwind {
-;CHECKIZFH-LABEL: fdiv_s:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: fdiv.h fa0, fa0, fa1
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fdiv_s:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fdiv.h fa0, fa0, fa1
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fdiv_s:
; RV32I: # %bb.0:
@@ -260,10 +260,10 @@ define half @fdiv_s(half %a, half %b) nounwind {
declare half @llvm.sqrt.f16(half)
define half @fsqrt_s(half %a) nounwind {
-;CHECKIZFH-LABEL: fsqrt_s:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: fsqrt.h fa0, fa0
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fsqrt_s:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fsqrt.h fa0, fa0
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fsqrt_s:
; RV32I: # %bb.0:
@@ -297,10 +297,10 @@ define half @fsqrt_s(half %a) nounwind {
declare half @llvm.copysign.f16(half, half)
define half @fsgnj_s(half %a, half %b) nounwind {
-;CHECKIZFH-LABEL: fsgnj_s:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: fsgnj.h fa0, fa0, fa1
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fsgnj_s:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fsgnj.h fa0, fa0, fa1
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fsgnj_s:
; RV32I: # %bb.0:
@@ -326,12 +326,12 @@ define half @fsgnj_s(half %a, half %b) nounwind {
; This function performs extra work to ensure that
; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
define i32 @fneg_s(half %a, half %b) nounwind {
-;CHECKIZFH-LABEL: fneg_s:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: fadd.h ft0, fa0, fa0
-;CHECKIZFH-NEXT: fneg.h ft1, ft0
-;CHECKIZFH-NEXT: feq.h a0, ft0, ft1
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fneg_s:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fadd.h ft0, fa0, fa0
+; CHECKIZFH-NEXT: fneg.h ft1, ft0
+; CHECKIZFH-NEXT: feq.h a0, ft0, ft1
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fneg_s:
; RV32I: # %bb.0:
@@ -404,11 +404,11 @@ define i32 @fneg_s(half %a, half %b) nounwind {
; This function performs extra work to ensure that
; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
define half @fsgnjn_s(half %a, half %b) nounwind {
-;CHECKIZFH-LABEL: fsgnjn_s:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: fadd.h ft0, fa0, fa1
-;CHECKIZFH-NEXT: fsgnjn.h fa0, fa0, ft0
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fsgnjn_s:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fadd.h ft0, fa0, fa1
+; CHECKIZFH-NEXT: fsgnjn.h fa0, fa0, ft0
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fsgnjn_s:
; RV32I: # %bb.0:
@@ -498,12 +498,12 @@ declare half @llvm.fabs.f16(half)
; This function performs extra work to ensure that
; DAGCombiner::visitBITCAST doesn't replace the fabs with an and.
define half @fabs_s(half %a, half %b) nounwind {
-;CHECKIZFH-LABEL: fabs_s:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: fadd.h ft0, fa0, fa1
-;CHECKIZFH-NEXT: fabs.h ft1, ft0
-;CHECKIZFH-NEXT: fadd.h fa0, ft1, ft0
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fabs_s:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fadd.h ft0, fa0, fa1
+; CHECKIZFH-NEXT: fabs.h ft1, ft0
+; CHECKIZFH-NEXT: fadd.h fa0, ft1, ft0
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fabs_s:
; RV32I: # %bb.0:
@@ -587,10 +587,10 @@ define half @fabs_s(half %a, half %b) nounwind {
declare half @llvm.minnum.f16(half, half)
define half @fmin_s(half %a, half %b) nounwind {
-;CHECKIZFH-LABEL: fmin_s:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: fmin.h fa0, fa0, fa1
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fmin_s:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fmin.h fa0, fa0, fa1
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fmin_s:
; RV32I: # %bb.0:
@@ -650,10 +650,10 @@ define half @fmin_s(half %a, half %b) nounwind {
declare half @llvm.maxnum.f16(half, half)
define half @fmax_s(half %a, half %b) nounwind {
-;CHECKIZFH-LABEL: fmax_s:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: fmax.h fa0, fa0, fa1
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fmax_s:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fmax.h fa0, fa0, fa1
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fmax_s:
; RV32I: # %bb.0:
@@ -713,10 +713,10 @@ define half @fmax_s(half %a, half %b) nounwind {
declare half @llvm.fma.f16(half, half, half)
define half @fmadd_s(half %a, half %b, half %c) nounwind {
-;CHECKIZFH-LABEL: fmadd_s:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fmadd_s:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fmadd_s:
; RV32I: # %bb.0:
@@ -788,12 +788,12 @@ define half @fmadd_s(half %a, half %b, half %c) nounwind {
}
define half @fmsub_s(half %a, half %b, half %c) nounwind {
-;CHECKIZFH-LABEL: fmsub_s:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: fmv.h.x ft0, zero
-;CHECKIZFH-NEXT: fadd.h ft0, fa2, ft0
-;CHECKIZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fmsub_s:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fmv.h.x ft0, zero
+; CHECKIZFH-NEXT: fadd.h ft0, fa2, ft0
+; CHECKIZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fmsub_s:
; RV32I: # %bb.0:
@@ -889,13 +889,13 @@ define half @fmsub_s(half %a, half %b, half %c) nounwind {
}
define half @fnmadd_s(half %a, half %b, half %c) nounwind {
-;CHECKIZFH-LABEL: fnmadd_s:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: fmv.h.x ft0, zero
-;CHECKIZFH-NEXT: fadd.h ft1, fa0, ft0
-;CHECKIZFH-NEXT: fadd.h ft0, fa2, ft0
-;CHECKIZFH-NEXT: fnmadd.h fa0, ft1, fa1, ft0
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fnmadd_s:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fmv.h.x ft0, zero
+; CHECKIZFH-NEXT: fadd.h ft1, fa0, ft0
+; CHECKIZFH-NEXT: fadd.h ft0, fa2, ft0
+; CHECKIZFH-NEXT: fnmadd.h fa0, ft1, fa1, ft0
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fnmadd_s:
; RV32I: # %bb.0:
@@ -1021,13 +1021,13 @@ define half @fnmadd_s(half %a, half %b, half %c) nounwind {
}
define half @fnmadd_s_2(half %a, half %b, half %c) nounwind {
-;CHECKIZFH-LABEL: fnmadd_s_2:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: fmv.h.x ft0, zero
-;CHECKIZFH-NEXT: fadd.h ft1, fa1, ft0
-;CHECKIZFH-NEXT: fadd.h ft0, fa2, ft0
-;CHECKIZFH-NEXT: fnmadd.h fa0, ft1, fa0, ft0
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fnmadd_s_2:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fmv.h.x ft0, zero
+; CHECKIZFH-NEXT: fadd.h ft1, fa1, ft0
+; CHECKIZFH-NEXT: fadd.h ft0, fa2, ft0
+; CHECKIZFH-NEXT: fnmadd.h fa0, ft1, fa0, ft0
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fnmadd_s_2:
; RV32I: # %bb.0:
@@ -1165,6 +1165,12 @@ define half @fnmadd_s_3(half %a, half %b, half %c) nounwind {
; RV64IZFH-NEXT: fneg.h fa0, ft0
; RV64IZFH-NEXT: ret
;
+; CHECKIZFH-LABEL: fnmadd_s_3:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fmadd.h ft0, fa0, fa1, fa2
+; CHECKIZFH-NEXT: fneg.h fa0, ft0
+; CHECKIZFH-NEXT: ret
+;
; RV32I-LABEL: fnmadd_s_3:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
@@ -1251,6 +1257,11 @@ define half @fnmadd_nsz(half %a, half %b, half %c) nounwind {
; RV64IZFH-NEXT: fnmadd.h fa0, fa0, fa1, fa2
; RV64IZFH-NEXT: ret
;
+; CHECKIZFH-LABEL: fnmadd_nsz:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fnmadd.h fa0, fa0, fa1, fa2
+; CHECKIZFH-NEXT: ret
+;
; RV32I-LABEL: fnmadd_nsz:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
@@ -1326,12 +1337,12 @@ define half @fnmadd_nsz(half %a, half %b, half %c) nounwind {
}
define half @fnmsub_s(half %a, half %b, half %c) nounwind {
-;CHECKIZFH-LABEL: fnmsub_s:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: fmv.h.x ft0, zero
-;CHECKIZFH-NEXT: fadd.h ft0, fa0, ft0
-;CHECKIZFH-NEXT: fnmsub.h fa0, ft0, fa1, fa2
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fnmsub_s:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fmv.h.x ft0, zero
+; CHECKIZFH-NEXT: fadd.h ft0, fa0, ft0
+; CHECKIZFH-NEXT: fnmsub.h fa0, ft0, fa1, fa2
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fnmsub_s:
; RV32I: # %bb.0:
@@ -1425,12 +1436,12 @@ define half @fnmsub_s(half %a, half %b, half %c) nounwind {
}
define half @fnmsub_s_2(half %a, half %b, half %c) nounwind {
-;CHECKIZFH-LABEL: fnmsub_s_2:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: fmv.h.x ft0, zero
-;CHECKIZFH-NEXT: fadd.h ft0, fa1, ft0
-;CHECKIZFH-NEXT: fnmsub.h fa0, ft0, fa0, fa2
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fnmsub_s_2:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fmv.h.x ft0, zero
+; CHECKIZFH-NEXT: fadd.h ft0, fa1, ft0
+; CHECKIZFH-NEXT: fnmsub.h fa0, ft0, fa0, fa2
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fnmsub_s_2:
; RV32I: # %bb.0:
@@ -1526,10 +1537,10 @@ define half @fnmsub_s_2(half %a, half %b, half %c) nounwind {
}
define half @fmadd_s_contract(half %a, half %b, half %c) nounwind {
-;CHECKIZFH-LABEL: fmadd_s_contract:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fmadd_s_contract:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fmadd_s_contract:
; RV32I: # %bb.0:
@@ -1612,12 +1623,12 @@ define half @fmadd_s_contract(half %a, half %b, half %c) nounwind {
}
define half @fmsub_s_contract(half %a, half %b, half %c) nounwind {
-;CHECKIZFH-LABEL: fmsub_s_contract:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: fmv.h.x ft0, zero
-;CHECKIZFH-NEXT: fadd.h ft0, fa2, ft0
-;CHECKIZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fmsub_s_contract:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fmv.h.x ft0, zero
+; CHECKIZFH-NEXT: fadd.h ft0, fa2, ft0
+; CHECKIZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fmsub_s_contract:
; RV32I: # %bb.0:
@@ -1713,14 +1724,14 @@ define half @fmsub_s_contract(half %a, half %b, half %c) nounwind {
}
define half @fnmadd_s_contract(half %a, half %b, half %c) nounwind {
-;CHECKIZFH-LABEL: fnmadd_s_contract:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: fmv.h.x ft0, zero
-;CHECKIZFH-NEXT: fadd.h ft1, fa0, ft0
-;CHECKIZFH-NEXT: fadd.h ft2, fa1, ft0
-;CHECKIZFH-NEXT: fadd.h ft0, fa2, ft0
-;CHECKIZFH-NEXT: fnmadd.h fa0, ft1, ft2, ft0
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fnmadd_s_contract:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fmv.h.x ft0, zero
+; CHECKIZFH-NEXT: fadd.h ft1, fa0, ft0
+; CHECKIZFH-NEXT: fadd.h ft2, fa1, ft0
+; CHECKIZFH-NEXT: fadd.h ft0, fa2, ft0
+; CHECKIZFH-NEXT: fnmadd.h fa0, ft1, ft2, ft0
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fnmadd_s_contract:
; RV32I: # %bb.0:
@@ -1853,13 +1864,13 @@ define half @fnmadd_s_contract(half %a, half %b, half %c) nounwind {
}
define half @fnmsub_s_contract(half %a, half %b, half %c) nounwind {
-;CHECKIZFH-LABEL: fnmsub_s_contract:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: fmv.h.x ft0, zero
-;CHECKIZFH-NEXT: fadd.h ft1, fa0, ft0
-;CHECKIZFH-NEXT: fadd.h ft0, fa1, ft0
-;CHECKIZFH-NEXT: fnmsub.h fa0, ft1, ft0, fa2
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fnmsub_s_contract:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fmv.h.x ft0, zero
+; CHECKIZFH-NEXT: fadd.h ft1, fa0, ft0
+; CHECKIZFH-NEXT: fadd.h ft0, fa1, ft0
+; CHECKIZFH-NEXT: fnmsub.h fa0, ft1, ft0, fa2
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fnmsub_s_contract:
; RV32I: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/half-fcmp.ll b/llvm/test/CodeGen/RISCV/half-fcmp.ll
index 7c84c9607bb8e..eb3b1625642e9 100644
--- a/llvm/test/CodeGen/RISCV/half-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/half-fcmp.ll
@@ -9,10 +9,10 @@
; RUN: < %s | FileCheck -check-prefix=RV64I %s
define i32 @fcmp_false(half %a, half %b) nounwind {
-;CHECKIZFH-LABEL: fcmp_false:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: li a0, 0
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcmp_false:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: li a0, 0
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_false:
; RV32I: # %bb.0:
@@ -29,10 +29,10 @@ define i32 @fcmp_false(half %a, half %b) nounwind {
}
define i32 @fcmp_oeq(half %a, half %b) nounwind {
-;CHECKIZFH-LABEL: fcmp_oeq:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: feq.h a0, fa0, fa1
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcmp_oeq:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: feq.h a0, fa0, fa1
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_oeq:
; RV32I: # %bb.0:
@@ -53,10 +53,10 @@ define i32 @fcmp_oeq(half %a, half %b) nounwind {
}
define i32 @fcmp_ogt(half %a, half %b) nounwind {
-;CHECKIZFH-LABEL: fcmp_ogt:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: flt.h a0, fa1, fa0
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcmp_ogt:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: flt.h a0, fa1, fa0
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_ogt:
; RV32I: # %bb.0:
@@ -77,10 +77,10 @@ define i32 @fcmp_ogt(half %a, half %b) nounwind {
}
define i32 @fcmp_oge(half %a, half %b) nounwind {
-;CHECKIZFH-LABEL: fcmp_oge:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: fle.h a0, fa1, fa0
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcmp_oge:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fle.h a0, fa1, fa0
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_oge:
; RV32I: # %bb.0:
@@ -101,10 +101,10 @@ define i32 @fcmp_oge(half %a, half %b) nounwind {
}
define i32 @fcmp_olt(half %a, half %b) nounwind {
-;CHECKIZFH-LABEL: fcmp_olt:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: flt.h a0, fa0, fa1
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcmp_olt:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: flt.h a0, fa0, fa1
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_olt:
; RV32I: # %bb.0:
@@ -125,10 +125,10 @@ define i32 @fcmp_olt(half %a, half %b) nounwind {
}
define i32 @fcmp_ole(half %a, half %b) nounwind {
-;CHECKIZFH-LABEL: fcmp_ole:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: fle.h a0, fa0, fa1
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcmp_ole:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fle.h a0, fa0, fa1
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_ole:
; RV32I: # %bb.0:
@@ -149,12 +149,12 @@ define i32 @fcmp_ole(half %a, half %b) nounwind {
}
define i32 @fcmp_one(half %a, half %b) nounwind {
-;CHECKIZFH-LABEL: fcmp_one:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: flt.h a0, fa0, fa1
-;CHECKIZFH-NEXT: flt.h a1, fa1, fa0
-;CHECKIZFH-NEXT: or a0, a1, a0
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcmp_one:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: flt.h a0, fa0, fa1
+; CHECKIZFH-NEXT: flt.h a1, fa1, fa0
+; CHECKIZFH-NEXT: or a0, a1, a0
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_one:
; RV32I: # %bb.0:
@@ -179,12 +179,12 @@ define i32 @fcmp_one(half %a, half %b) nounwind {
}
define i32 @fcmp_ord(half %a, half %b) nounwind {
-;CHECKIZFH-LABEL: fcmp_ord:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: feq.h a0, fa1, fa1
-;CHECKIZFH-NEXT: feq.h a1, fa0, fa0
-;CHECKIZFH-NEXT: and a0, a1, a0
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcmp_ord:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: feq.h a0, fa1, fa1
+; CHECKIZFH-NEXT: feq.h a1, fa0, fa0
+; CHECKIZFH-NEXT: and a0, a1, a0
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_ord:
; RV32I: # %bb.0:
@@ -209,13 +209,13 @@ define i32 @fcmp_ord(half %a, half %b) nounwind {
}
define i32 @fcmp_ueq(half %a, half %b) nounwind {
-;CHECKIZFH-LABEL: fcmp_ueq:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: flt.h a0, fa0, fa1
-;CHECKIZFH-NEXT: flt.h a1, fa1, fa0
-;CHECKIZFH-NEXT: or a0, a1, a0
-;CHECKIZFH-NEXT: xori a0, a0, 1
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcmp_ueq:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: flt.h a0, fa0, fa1
+; CHECKIZFH-NEXT: flt.h a1, fa1, fa0
+; CHECKIZFH-NEXT: or a0, a1, a0
+; CHECKIZFH-NEXT: xori a0, a0, 1
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_ueq:
; RV32I: # %bb.0:
@@ -242,11 +242,11 @@ define i32 @fcmp_ueq(half %a, half %b) nounwind {
}
define i32 @fcmp_ugt(half %a, half %b) nounwind {
-;CHECKIZFH-LABEL: fcmp_ugt:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: fle.h a0, fa0, fa1
-;CHECKIZFH-NEXT: xori a0, a0, 1
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcmp_ugt:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fle.h a0, fa0, fa1
+; CHECKIZFH-NEXT: xori a0, a0, 1
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_ugt:
; RV32I: # %bb.0:
@@ -269,11 +269,11 @@ define i32 @fcmp_ugt(half %a, half %b) nounwind {
}
define i32 @fcmp_uge(half %a, half %b) nounwind {
-;CHECKIZFH-LABEL: fcmp_uge:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: flt.h a0, fa0, fa1
-;CHECKIZFH-NEXT: xori a0, a0, 1
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcmp_uge:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: flt.h a0, fa0, fa1
+; CHECKIZFH-NEXT: xori a0, a0, 1
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_uge:
; RV32I: # %bb.0:
@@ -296,11 +296,11 @@ define i32 @fcmp_uge(half %a, half %b) nounwind {
}
define i32 @fcmp_ult(half %a, half %b) nounwind {
-;CHECKIZFH-LABEL: fcmp_ult:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: fle.h a0, fa1, fa0
-;CHECKIZFH-NEXT: xori a0, a0, 1
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcmp_ult:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: fle.h a0, fa1, fa0
+; CHECKIZFH-NEXT: xori a0, a0, 1
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_ult:
; RV32I: # %bb.0:
@@ -323,11 +323,11 @@ define i32 @fcmp_ult(half %a, half %b) nounwind {
}
define i32 @fcmp_ule(half %a, half %b) nounwind {
-;CHECKIZFH-LABEL: fcmp_ule:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: flt.h a0, fa1, fa0
-;CHECKIZFH-NEXT: xori a0, a0, 1
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcmp_ule:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: flt.h a0, fa1, fa0
+; CHECKIZFH-NEXT: xori a0, a0, 1
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_ule:
; RV32I: # %bb.0:
@@ -350,11 +350,11 @@ define i32 @fcmp_ule(half %a, half %b) nounwind {
}
define i32 @fcmp_une(half %a, half %b) nounwind {
-;CHECKIZFH-LABEL: fcmp_une:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: feq.h a0, fa0, fa1
-;CHECKIZFH-NEXT: xori a0, a0, 1
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcmp_une:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: feq.h a0, fa0, fa1
+; CHECKIZFH-NEXT: xori a0, a0, 1
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_une:
; RV32I: # %bb.0:
@@ -377,13 +377,13 @@ define i32 @fcmp_une(half %a, half %b) nounwind {
}
define i32 @fcmp_uno(half %a, half %b) nounwind {
-;CHECKIZFH-LABEL: fcmp_uno:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: feq.h a0, fa1, fa1
-;CHECKIZFH-NEXT: feq.h a1, fa0, fa0
-;CHECKIZFH-NEXT: and a0, a1, a0
-;CHECKIZFH-NEXT: xori a0, a0, 1
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcmp_uno:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: feq.h a0, fa1, fa1
+; CHECKIZFH-NEXT: feq.h a1, fa0, fa0
+; CHECKIZFH-NEXT: and a0, a1, a0
+; CHECKIZFH-NEXT: xori a0, a0, 1
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_uno:
; RV32I: # %bb.0:
@@ -410,10 +410,10 @@ define i32 @fcmp_uno(half %a, half %b) nounwind {
}
define i32 @fcmp_true(half %a, half %b) nounwind {
-;CHECKIZFH-LABEL: fcmp_true:
-;CHECKIZFH: # %bb.0:
-;CHECKIZFH-NEXT: li a0, 1
-;CHECKIZFH-NEXT: ret
+; CHECKIZFH-LABEL: fcmp_true:
+; CHECKIZFH: # %bb.0:
+; CHECKIZFH-NEXT: li a0, 1
+; CHECKIZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_true:
; RV32I: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/rv32zknd-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv32zknd-intrinsic.ll
index 2f7d2a2f07d91..33c5839fde586 100644
--- a/llvm/test/CodeGen/RISCV/rv32zknd-intrinsic.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zknd-intrinsic.ll
@@ -5,10 +5,10 @@
declare i32 @llvm.riscv.aes32dsi(i32, i32, i8);
define i32 @aes32dsi(i32 %a, i32 %b) nounwind {
-; RV32ZKND-LABEL: aes32dsi
-; RV32ZKND: # %bb.0:
-; RV32ZKND-NEXT: aes32dsi a0, a0, a1, 0
-; RV32ZKND-NEXT: ret
+; RV32ZKND-LABEL: aes32dsi:
+; RV32ZKND: # %bb.0:
+; RV32ZKND-NEXT: aes32dsi a0, a0, a1, 0
+; RV32ZKND-NEXT: ret
%val = call i32 @llvm.riscv.aes32dsi(i32 %a, i32 %b, i8 0)
ret i32 %val
}
@@ -16,10 +16,10 @@ define i32 @aes32dsi(i32 %a, i32 %b) nounwind {
declare i32 @llvm.riscv.aes32dsmi(i32, i32, i8);
define i32 @aes32dsmi(i32 %a, i32 %b) nounwind {
-; RV32ZKND-LABEL: aes32dsmi
-; RV32ZKND: # %bb.0:
-; RV32ZKND-NEXT: aes32dsmi a0, a0, a1, 1
-; RV32ZKND-NEXT: ret
+; RV32ZKND-LABEL: aes32dsmi:
+; RV32ZKND: # %bb.0:
+; RV32ZKND-NEXT: aes32dsmi a0, a0, a1, 1
+; RV32ZKND-NEXT: ret
%val = call i32 @llvm.riscv.aes32dsmi(i32 %a, i32 %b, i8 1)
ret i32 %val
}
diff --git a/llvm/test/CodeGen/RISCV/rv32zkne-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv32zkne-intrinsic.ll
index 3b8937b2549da..296641ca593e6 100644
--- a/llvm/test/CodeGen/RISCV/rv32zkne-intrinsic.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zkne-intrinsic.ll
@@ -5,10 +5,10 @@
declare i32 @llvm.riscv.aes32esi(i32, i32, i8);
define i32 @aes32esi(i32 %a, i32 %b) nounwind {
-; RV32ZKNE-LABEL: aes32esi
-; RV32ZKNE: # %bb.0:
-; RV32ZKNE-NEXT: aes32esi a0, a0, a1, 2
-; RV32ZKNE-NEXT: ret
+; RV32ZKNE-LABEL: aes32esi:
+; RV32ZKNE: # %bb.0:
+; RV32ZKNE-NEXT: aes32esi a0, a0, a1, 2
+; RV32ZKNE-NEXT: ret
%val = call i32 @llvm.riscv.aes32esi(i32 %a, i32 %b, i8 2)
ret i32 %val
}
@@ -16,10 +16,10 @@ define i32 @aes32esi(i32 %a, i32 %b) nounwind {
declare i32 @llvm.riscv.aes32esmi(i32, i32, i8);
define i32 @aes32esmi(i32 %a, i32 %b) nounwind {
-; RV32ZKNE-LABEL: aes32esmi
-; RV32ZKNE: # %bb.0:
-; RV32ZKNE-NEXT: aes32esmi a0, a0, a1, 3
-; RV32ZKNE-NEXT: ret
+; RV32ZKNE-LABEL: aes32esmi:
+; RV32ZKNE: # %bb.0:
+; RV32ZKNE-NEXT: aes32esmi a0, a0, a1, 3
+; RV32ZKNE-NEXT: ret
%val = call i32 @llvm.riscv.aes32esmi(i32 %a, i32 %b, i8 3)
ret i32 %val
}
diff --git a/llvm/test/CodeGen/RISCV/rv32zknh-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv32zknh-intrinsic.ll
index f6be9f012e85c..cc505709d7756 100644
--- a/llvm/test/CodeGen/RISCV/rv32zknh-intrinsic.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zknh-intrinsic.ll
@@ -6,10 +6,10 @@
declare i32 @llvm.riscv.sha256sig0.i32(i32);
define i32 @sha256sig0_i32(i32 %a) nounwind {
-; RV32ZKNH-LABEL: sha256sig0_i32
-; RV32ZKNH: # %bb.0:
-; RV32ZKNH-NEXT: sha256sig0 a0, a0
-; RV32ZKNH-NEXT: ret
+; RV32ZKNH-LABEL: sha256sig0_i32:
+; RV32ZKNH: # %bb.0:
+; RV32ZKNH-NEXT: sha256sig0 a0, a0
+; RV32ZKNH-NEXT: ret
%val = call i32 @llvm.riscv.sha256sig0.i32(i32 %a)
ret i32 %val
}
@@ -17,10 +17,10 @@ define i32 @sha256sig0_i32(i32 %a) nounwind {
declare i32 @llvm.riscv.sha256sig1.i32(i32);
define i32 @sha256sig1_i32(i32 %a) nounwind {
-; RV32ZKNH-LABEL: sha256sig1_i32
-; RV32ZKNH: # %bb.0:
-; RV32ZKNH-NEXT: sha256sig1 a0, a0
-; RV32ZKNH-NEXT: ret
+; RV32ZKNH-LABEL: sha256sig1_i32:
+; RV32ZKNH: # %bb.0:
+; RV32ZKNH-NEXT: sha256sig1 a0, a0
+; RV32ZKNH-NEXT: ret
%val = call i32 @llvm.riscv.sha256sig1.i32(i32 %a)
ret i32 %val
}
@@ -28,10 +28,10 @@ define i32 @sha256sig1_i32(i32 %a) nounwind {
declare i32 @llvm.riscv.sha256sum0.i32(i32);
define i32 @sha256sum0_i32(i32 %a) nounwind {
-; RV32ZKNH-LABEL: sha256sum0_i32
-; RV32ZKNH: # %bb.0:
-; RV32ZKNH-NEXT: sha256sum0 a0, a0
-; RV32ZKNH-NEXT: ret
+; RV32ZKNH-LABEL: sha256sum0_i32:
+; RV32ZKNH: # %bb.0:
+; RV32ZKNH-NEXT: sha256sum0 a0, a0
+; RV32ZKNH-NEXT: ret
%val = call i32 @llvm.riscv.sha256sum0.i32(i32 %a)
ret i32 %val
}
@@ -39,10 +39,10 @@ define i32 @sha256sum0_i32(i32 %a) nounwind {
declare i32 @llvm.riscv.sha256sum1.i32(i32);
define i32 @sha256sum1_i32(i32 %a) nounwind {
-; RV32ZKNH-LABEL: sha256sum1_i32
-; RV32ZKNH: # %bb.0:
-; RV32ZKNH-NEXT: sha256sum1 a0, a0
-; RV32ZKNH-NEXT: ret
+; RV32ZKNH-LABEL: sha256sum1_i32:
+; RV32ZKNH: # %bb.0:
+; RV32ZKNH-NEXT: sha256sum1 a0, a0
+; RV32ZKNH-NEXT: ret
%val = call i32 @llvm.riscv.sha256sum1.i32(i32 %a)
ret i32 %val
}
@@ -50,10 +50,10 @@ define i32 @sha256sum1_i32(i32 %a) nounwind {
declare i32 @llvm.riscv.sha512sig0l(i32, i32);
define i32 @sha512sig0l(i32 %a, i32 %b) nounwind {
-; RV32ZKNH-LABEL: sha512sig0l
-; RV32ZKNH: # %bb.0:
-; RV32ZKNH-NEXT: sha512sig0l a0, a0, a1
-; RV32ZKNH-NEXT: ret
+; RV32ZKNH-LABEL: sha512sig0l:
+; RV32ZKNH: # %bb.0:
+; RV32ZKNH-NEXT: sha512sig0l a0, a0, a1
+; RV32ZKNH-NEXT: ret
%val = call i32 @llvm.riscv.sha512sig0l(i32 %a, i32 %b)
ret i32 %val
}
@@ -61,10 +61,10 @@ define i32 @sha512sig0l(i32 %a, i32 %b) nounwind {
declare i32 @llvm.riscv.sha512sig0h(i32, i32);
define i32 @sha512sig0h(i32 %a, i32 %b) nounwind {
-; RV32ZKNH-LABEL: sha512sig0h
-; RV32ZKNH: # %bb.0:
-; RV32ZKNH-NEXT: sha512sig0h a0, a0, a1
-; RV32ZKNH-NEXT: ret
+; RV32ZKNH-LABEL: sha512sig0h:
+; RV32ZKNH: # %bb.0:
+; RV32ZKNH-NEXT: sha512sig0h a0, a0, a1
+; RV32ZKNH-NEXT: ret
%val = call i32 @llvm.riscv.sha512sig0h(i32 %a, i32 %b)
ret i32 %val
}
@@ -72,10 +72,10 @@ define i32 @sha512sig0h(i32 %a, i32 %b) nounwind {
declare i32 @llvm.riscv.sha512sig1l(i32, i32);
define i32 @sha512sig1l(i32 %a, i32 %b) nounwind {
-; RV32ZKNH-LABEL: sha512sig1l
-; RV32ZKNH: # %bb.0:
-; RV32ZKNH-NEXT: sha512sig1l a0, a0, a1
-; RV32ZKNH-NEXT: ret
+; RV32ZKNH-LABEL: sha512sig1l:
+; RV32ZKNH: # %bb.0:
+; RV32ZKNH-NEXT: sha512sig1l a0, a0, a1
+; RV32ZKNH-NEXT: ret
%val = call i32 @llvm.riscv.sha512sig1l(i32 %a, i32 %b)
ret i32 %val
}
@@ -83,10 +83,10 @@ define i32 @sha512sig1l(i32 %a, i32 %b) nounwind {
declare i32 @llvm.riscv.sha512sig1h(i32, i32);
define i32 @sha512sig1h(i32 %a, i32 %b) nounwind {
-; RV32ZKNH-LABEL: sha512sig1h
-; RV32ZKNH: # %bb.0:
-; RV32ZKNH-NEXT: sha512sig1h a0, a0, a1
-; RV32ZKNH-NEXT: ret
+; RV32ZKNH-LABEL: sha512sig1h:
+; RV32ZKNH: # %bb.0:
+; RV32ZKNH-NEXT: sha512sig1h a0, a0, a1
+; RV32ZKNH-NEXT: ret
%val = call i32 @llvm.riscv.sha512sig1h(i32 %a, i32 %b)
ret i32 %val
}
@@ -94,10 +94,10 @@ define i32 @sha512sig1h(i32 %a, i32 %b) nounwind {
declare i32 @llvm.riscv.sha512sum0r(i32, i32);
define i32 @sha512sum0r(i32 %a, i32 %b) nounwind {
-; RV32ZKNH-LABEL: sha512sum0r
-; RV32ZKNH: # %bb.0:
-; RV32ZKNH-NEXT: sha512sum0r a0, a0, a1
-; RV32ZKNH-NEXT: ret
+; RV32ZKNH-LABEL: sha512sum0r:
+; RV32ZKNH: # %bb.0:
+; RV32ZKNH-NEXT: sha512sum0r a0, a0, a1
+; RV32ZKNH-NEXT: ret
%val = call i32 @llvm.riscv.sha512sum0r(i32 %a, i32 %b)
ret i32 %val
}
@@ -105,10 +105,10 @@ define i32 @sha512sum0r(i32 %a, i32 %b) nounwind {
declare i32 @llvm.riscv.sha512sum1r(i32, i32);
define i32 @sha512sum1r(i32 %a, i32 %b) nounwind {
-; RV32ZKNH-LABEL: sha512sum1r
-; RV32ZKNH: # %bb.0:
-; RV32ZKNH-NEXT: sha512sum1r a0, a0, a1
-; RV32ZKNH-NEXT: ret
+; RV32ZKNH-LABEL: sha512sum1r:
+; RV32ZKNH: # %bb.0:
+; RV32ZKNH-NEXT: sha512sum1r a0, a0, a1
+; RV32ZKNH-NEXT: ret
%val = call i32 @llvm.riscv.sha512sum1r(i32 %a, i32 %b)
ret i32 %val
}
diff --git a/llvm/test/CodeGen/RISCV/rv64zknd-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv64zknd-intrinsic.ll
index 230ae7134e457..ea922ed6775a0 100644
--- a/llvm/test/CodeGen/RISCV/rv64zknd-intrinsic.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zknd-intrinsic.ll
@@ -5,10 +5,10 @@
declare i64 @llvm.riscv.aes64ds(i64, i64);
define i64 @aes64ds(i64 %a, i64 %b) nounwind {
-; RV64ZKND-LABEL: aes64ds
-; RV64ZKND: # %bb.0:
-; RV64ZKND-NEXT: aes64ds a0, a0, a1
-; RV64ZKND-NEXT: ret
+; RV64ZKND-LABEL: aes64ds:
+; RV64ZKND: # %bb.0:
+; RV64ZKND-NEXT: aes64ds a0, a0, a1
+; RV64ZKND-NEXT: ret
%val = call i64 @llvm.riscv.aes64ds(i64 %a, i64 %b)
ret i64 %val
}
@@ -16,10 +16,10 @@ define i64 @aes64ds(i64 %a, i64 %b) nounwind {
declare i64 @llvm.riscv.aes64dsm(i64, i64);
define i64 @aes64dsm(i64 %a, i64 %b) nounwind {
-; RV64ZKND-LABEL: aes64dsm
-; RV64ZKND: # %bb.0:
-; RV64ZKND-NEXT: aes64dsm a0, a0, a1
-; RV64ZKND-NEXT: ret
+; RV64ZKND-LABEL: aes64dsm:
+; RV64ZKND: # %bb.0:
+; RV64ZKND-NEXT: aes64dsm a0, a0, a1
+; RV64ZKND-NEXT: ret
%val = call i64 @llvm.riscv.aes64dsm(i64 %a, i64 %b)
ret i64 %val
}
@@ -27,10 +27,10 @@ define i64 @aes64dsm(i64 %a, i64 %b) nounwind {
declare i64 @llvm.riscv.aes64im(i64);
define i64 @aes64im(i64 %a) nounwind {
-; RV64ZKND-LABEL: aes64im
-; RV64ZKND: # %bb.0:
-; RV64ZKND-NEXT: aes64im a0, a0
-; RV64ZKND-NEXT: ret
+; RV64ZKND-LABEL: aes64im:
+; RV64ZKND: # %bb.0:
+; RV64ZKND-NEXT: aes64im a0, a0
+; RV64ZKND-NEXT: ret
%val = call i64 @llvm.riscv.aes64im(i64 %a)
ret i64 %val
}
diff --git a/llvm/test/CodeGen/RISCV/rv64zknd-zkne-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv64zknd-zkne-intrinsic.ll
index 23559b97410ee..075097037a5b3 100644
--- a/llvm/test/CodeGen/RISCV/rv64zknd-zkne-intrinsic.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zknd-zkne-intrinsic.ll
@@ -1,17 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+zknd -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64ZKND-ZKNE
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+zkne -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64ZKND-ZKNE
declare i64 @llvm.riscv.aes64ks2(i64, i64);
define i64 @aes64ks2(i64 %a, i64 %b) nounwind {
-; RV64ZKND-ZKNE-LABEL: aes64ks2
-; RV64ZKND-ZKNE: # %bb.0:
-; RV64ZKND-ZKNE-NEXT: aes64ks2 a0, a0, a1
-; RV64ZKND-ZKNE-NEXT: ret
+; RV64ZKND-ZKNE-LABEL: aes64ks2:
+; RV64ZKND-ZKNE: # %bb.0:
+; RV64ZKND-ZKNE-NEXT: aes64ks2 a0, a0, a1
+; RV64ZKND-ZKNE-NEXT: ret
%val = call i64 @llvm.riscv.aes64ks2(i64 %a, i64 %b)
ret i64 %val
}
@@ -19,10 +18,10 @@ define i64 @aes64ks2(i64 %a, i64 %b) nounwind {
declare i64 @llvm.riscv.aes64ks1i(i64, i32);
define i64 @aes64ks1i(i64 %a) nounwind {
-; RV64ZKND-ZKNE-LABEL: aes64ks1i
-; RV64ZKND-ZKNE: # %bb.0:
-; RV64ZKND-ZKNE-NEXT: aes64ks1i a0, a0, 10
-; RV64ZKND-ZKNE-NEXT: ret
+; RV64ZKND-ZKNE-LABEL: aes64ks1i:
+; RV64ZKND-ZKNE: # %bb.0:
+; RV64ZKND-ZKNE-NEXT: aes64ks1i a0, a0, 10
+; RV64ZKND-ZKNE-NEXT: ret
%val = call i64 @llvm.riscv.aes64ks1i(i64 %a, i32 10)
ret i64 %val
}
diff --git a/llvm/test/CodeGen/RISCV/rv64zkne-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv64zkne-intrinsic.ll
index 1697769d2b9d4..eee03a0c4469b 100644
--- a/llvm/test/CodeGen/RISCV/rv64zkne-intrinsic.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zkne-intrinsic.ll
@@ -5,10 +5,10 @@
declare i64 @llvm.riscv.aes64es(i64, i64);
define i64 @aes64es(i64 %a, i64 %b) nounwind {
-; RV64ZKNE-LABEL: aes64es
-; RV64ZKNE: # %bb.0:
-; RV64ZKNE-NEXT: aes64es a0, a0, a1
-; RV64ZKNE-NEXT: ret
+; RV64ZKNE-LABEL: aes64es:
+; RV64ZKNE: # %bb.0:
+; RV64ZKNE-NEXT: aes64es a0, a0, a1
+; RV64ZKNE-NEXT: ret
%val = call i64 @llvm.riscv.aes64es(i64 %a, i64 %b)
ret i64 %val
}
@@ -16,10 +16,10 @@ define i64 @aes64es(i64 %a, i64 %b) nounwind {
declare i64 @llvm.riscv.aes64esm(i64, i64);
define i64 @aes64esm(i64 %a, i64 %b) nounwind {
-; RV64ZKNE-LABEL: aes64esm
-; RV64ZKNE: # %bb.0:
-; RV64ZKNE-NEXT: aes64esm a0, a0, a1
-; RV64ZKNE-NEXT: ret
+; RV64ZKNE-LABEL: aes64esm:
+; RV64ZKNE: # %bb.0:
+; RV64ZKNE-NEXT: aes64esm a0, a0, a1
+; RV64ZKNE-NEXT: ret
%val = call i64 @llvm.riscv.aes64esm(i64 %a, i64 %b)
ret i64 %val
}
diff --git a/llvm/test/CodeGen/RISCV/rv64zknh-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv64zknh-intrinsic.ll
index b77fe1c4cf7d2..b96524b3294fc 100644
--- a/llvm/test/CodeGen/RISCV/rv64zknh-intrinsic.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zknh-intrinsic.ll
@@ -6,10 +6,10 @@
declare i64 @llvm.riscv.sha256sig0.i64(i64);
define i64 @sha256sig0_i64(i64 %a) nounwind {
-; RV64ZKNH-LABEL: sha256sig0_i64
-; RV64ZKNH: # %bb.0:
-; RV64ZKNH-NEXT: sha256sig0 a0, a0
-; RV64ZKNH-NEXT: ret
+; RV64ZKNH-LABEL: sha256sig0_i64:
+; RV64ZKNH: # %bb.0:
+; RV64ZKNH-NEXT: sha256sig0 a0, a0
+; RV64ZKNH-NEXT: ret
%val = call i64 @llvm.riscv.sha256sig0.i64(i64 %a)
ret i64 %val
}
@@ -17,10 +17,10 @@ define i64 @sha256sig0_i64(i64 %a) nounwind {
declare i64 @llvm.riscv.sha256sig1.i64(i64);
define i64 @sha256sig1_i64(i64 %a) nounwind {
-; RV64ZKNH-LABEL: sha256sig1_i64
-; RV64ZKNH: # %bb.0:
-; RV64ZKNH-NEXT: sha256sig1 a0, a0
-; RV64ZKNH-NEXT: ret
+; RV64ZKNH-LABEL: sha256sig1_i64:
+; RV64ZKNH: # %bb.0:
+; RV64ZKNH-NEXT: sha256sig1 a0, a0
+; RV64ZKNH-NEXT: ret
%val = call i64 @llvm.riscv.sha256sig1.i64(i64 %a)
ret i64 %val
}
@@ -28,10 +28,10 @@ define i64 @sha256sig1_i64(i64 %a) nounwind {
declare i64 @llvm.riscv.sha256sum0.i64(i64);
define i64 @sha256sum0_i64(i64 %a) nounwind {
-; RV64ZKNH-LABEL: sha256sum0_i64
-; RV64ZKNH: # %bb.0:
-; RV64ZKNH-NEXT: sha256sum0 a0, a0
-; RV64ZKNH-NEXT: ret
+; RV64ZKNH-LABEL: sha256sum0_i64:
+; RV64ZKNH: # %bb.0:
+; RV64ZKNH-NEXT: sha256sum0 a0, a0
+; RV64ZKNH-NEXT: ret
%val = call i64 @llvm.riscv.sha256sum0.i64(i64 %a)
ret i64 %val
}
@@ -39,10 +39,10 @@ define i64 @sha256sum0_i64(i64 %a) nounwind {
declare i64 @llvm.riscv.sha256sum1.i64(i64);
define i64 @sha256sum1_i64(i64 %a) nounwind {
-; RV64ZKNH-LABEL: sha256sum1_i64
-; RV64ZKNH: # %bb.0:
-; RV64ZKNH-NEXT: sha256sum1 a0, a0
-; RV64ZKNH-NEXT: ret
+; RV64ZKNH-LABEL: sha256sum1_i64:
+; RV64ZKNH: # %bb.0:
+; RV64ZKNH-NEXT: sha256sum1 a0, a0
+; RV64ZKNH-NEXT: ret
%val = call i64 @llvm.riscv.sha256sum1.i64(i64 %a)
ret i64 %val
}
@@ -50,10 +50,10 @@ define i64 @sha256sum1_i64(i64 %a) nounwind {
declare i64 @llvm.riscv.sha512sig0(i64);
define i64 @sha512sig0(i64 %a) nounwind {
-; RV64ZKNH-LABEL: sha512sig0
-; RV64ZKNH: # %bb.0:
-; RV64ZKNH-NEXT: sha512sig0 a0, a0
-; RV64ZKNH-NEXT: ret
+; RV64ZKNH-LABEL: sha512sig0:
+; RV64ZKNH: # %bb.0:
+; RV64ZKNH-NEXT: sha512sig0 a0, a0
+; RV64ZKNH-NEXT: ret
%val = call i64 @llvm.riscv.sha512sig0(i64 %a)
ret i64 %val
}
@@ -61,10 +61,10 @@ define i64 @sha512sig0(i64 %a) nounwind {
declare i64 @llvm.riscv.sha512sig1(i64);
define i64 @sha512sig1(i64 %a) nounwind {
-; RV64ZKNH-LABEL: sha512sig1
-; RV64ZKNH: # %bb.0:
-; RV64ZKNH-NEXT: sha512sig1 a0, a0
-; RV64ZKNH-NEXT: ret
+; RV64ZKNH-LABEL: sha512sig1:
+; RV64ZKNH: # %bb.0:
+; RV64ZKNH-NEXT: sha512sig1 a0, a0
+; RV64ZKNH-NEXT: ret
%val = call i64 @llvm.riscv.sha512sig1(i64 %a)
ret i64 %val
}
@@ -72,10 +72,10 @@ define i64 @sha512sig1(i64 %a) nounwind {
declare i64 @llvm.riscv.sha512sum0(i64);
define i64 @sha512sum0(i64 %a) nounwind {
-; RV64ZKNH-LABEL: sha512sum0
-; RV64ZKNH: # %bb.0:
-; RV64ZKNH-NEXT: sha512sum0 a0, a0
-; RV64ZKNH-NEXT: ret
+; RV64ZKNH-LABEL: sha512sum0:
+; RV64ZKNH: # %bb.0:
+; RV64ZKNH-NEXT: sha512sum0 a0, a0
+; RV64ZKNH-NEXT: ret
%val = call i64 @llvm.riscv.sha512sum0(i64 %a)
ret i64 %val
}
@@ -83,10 +83,10 @@ define i64 @sha512sum0(i64 %a) nounwind {
declare i64 @llvm.riscv.sha512sum1(i64);
define i64 @sha512sum1(i64 %a) nounwind {
-; RV64ZKNH-LABEL: sha512sum1
-; RV64ZKNH: # %bb.0:
-; RV64ZKNH-NEXT: sha512sum1 a0, a0
-; RV64ZKNH-NEXT: ret
+; RV64ZKNH-LABEL: sha512sum1:
+; RV64ZKNH: # %bb.0:
+; RV64ZKNH-NEXT: sha512sum1 a0, a0
+; RV64ZKNH-NEXT: ret
%val = call i64 @llvm.riscv.sha512sum1(i64 %a)
ret i64 %val
}
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