[PATCH] D128252: [AMDGPU] Lowering VGPR to SGPR copies to v_readfirstlane_b32 if profitable.

[Alexander via Phabricator via llvm-commits]

alex-t marked an inline comment as done.
alex-t added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp:1119
+      " Score: " << C.second.Score << "\n");
+    uint16_t SubRegs[4] = {AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2,
+                            AMDGPU::sub3};
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foad wrote:
> Should be const. But why is 4 enough? Isn't there some way you can get this programmatically from SIRegisterInfo?
For now just SIRegisterInfo::getSubRegFromChannel is used. Later I would like to change the SIInstrInfo::readlaneVGPRToSGPR to serve all cases.


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  https://reviews.llvm.org/D128252/new/

https://reviews.llvm.org/D128252