[llvm] 9bc77b7 - [AArch64] Regenerate arm64-vselect.ll test checks

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2022-07-13T13:52:15+01:00
New Revision: 9bc77b734294d618cf3f0b5f0f36863f337186e1

URL: https://github.com/llvm/llvm-project/commit/9bc77b734294d618cf3f0b5f0f36863f337186e1
DIFF: https://github.com/llvm/llvm-project/commit/9bc77b734294d618cf3f0b5f0f36863f337186e1.diff

LOG: [AArch64] Regenerate arm64-vselect.ll test checks

The ushll -> sshll FIXME had been fixed long ago, but nobody noticed because the test wasn't checking for either.....

Added: 
    

Modified: 
    llvm/test/CodeGen/AArch64/arm64-vselect.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AArch64/arm64-vselect.ll b/llvm/test/CodeGen/AArch64/arm64-vselect.ll
index e48f2b29b9135..b843b8393ebda 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vselect.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vselect.ll
@@ -1,23 +1,17 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
 
-;CHECK: @func63
-;CHECK: cmeq.4h v0, v0, v1
-
-;FIXME: currently, it will generate 3 instructions:
-; ushll.4s	v0, v0, #0
-; shl.4s	v0, v0, #31
-; sshr.4s	v0, v0, #31
-;But these instrucitons can be optimized into 1 instruction:
-; sshll.4s  v0, v0, #0
-
-;CHECK: bsl.16b v0, v2, v3
-;CHECK: str  q0, [x0]
-;CHECK: ret
-
 %T0_63 = type <4 x i16>
 %T1_63 = type <4 x i32>
 %T2_63 = type <4 x i1>
 define void @func63(%T1_63* %out, %T0_63 %v0, %T0_63 %v1, %T1_63 %v2, %T1_63 %v3) {
+; CHECK-LABEL: func63:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmeq.4h v0, v0, v1
+; CHECK-NEXT:    sshll.4s v0, v0, #0
+; CHECK-NEXT:    bsl.16b v0, v2, v3
+; CHECK-NEXT:    str q0, [x0]
+; CHECK-NEXT:    ret
   %cond = icmp eq %T0_63 %v0, %v1
   %r = select %T2_63 %cond, %T1_63 %v2, %T1_63 %v3
   store %T1_63 %r, %T1_63* %out