[llvm] 9049c46 - [RISCV][test] Add test of binop followed by extractelement.
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 12 23:54:08 PDT 2022
Author: jacquesguan
Date: 2022-07-13T14:33:56+08:00
New Revision: 9049c46b9d0edaf25ddeb0697aca5f999346668c
URL: https://github.com/llvm/llvm-project/commit/9049c46b9d0edaf25ddeb0697aca5f999346668c
DIFF: https://github.com/llvm/llvm-project/commit/9049c46b9d0edaf25ddeb0697aca5f999346668c.diff
LOG: [RISCV][test] Add test of binop followed by extractelement.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D129544
Added:
Modified:
llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll
llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll
llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll
index 3bc8d9cc07b0..bad9991a6165 100644
--- a/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll
@@ -481,3 +481,73 @@ define double @extractelt_nxv8f64_idx(<vscale x 8 x double> %v, i32 %idx) {
%r = extractelement <vscale x 8 x double> %v, i32 %idx
ret double %r
}
+
+define float @extractelt_fadd_nxv4f32_splat(<vscale x 4 x float> %x) {
+; CHECK-LABEL: extractelt_fadd_nxv4f32_splat:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, %hi(.LCPI45_0)
+; CHECK-NEXT: flw ft0, %lo(.LCPI45_0)(a0)
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT: vfadd.vf v8, v8, ft0
+; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x float> poison, float 3.0, i32 0
+ %splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
+ %bo = fadd <vscale x 4 x float> %x, %splat
+ %ext = extractelement <vscale x 4 x float> %bo, i32 2
+ ret float %ext
+}
+
+define float @extractelt_fsub_nxv4f32_splat(<vscale x 4 x float> %x) {
+; CHECK-LABEL: extractelt_fsub_nxv4f32_splat:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, %hi(.LCPI46_0)
+; CHECK-NEXT: flw ft0, %lo(.LCPI46_0)(a0)
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT: vfrsub.vf v8, v8, ft0
+; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
+; CHECK-NEXT: vslidedown.vi v8, v8, 1
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x float> poison, float 3.0, i32 0
+ %splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
+ %bo = fsub <vscale x 4 x float> %splat, %x
+ %ext = extractelement <vscale x 4 x float> %bo, i32 1
+ ret float %ext
+}
+
+define float @extractelt_fmul_nxv4f32_splat(<vscale x 4 x float> %x) {
+; CHECK-LABEL: extractelt_fmul_nxv4f32_splat:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, %hi(.LCPI47_0)
+; CHECK-NEXT: flw ft0, %lo(.LCPI47_0)(a0)
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT: vfmul.vf v8, v8, ft0
+; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
+; CHECK-NEXT: vslidedown.vi v8, v8, 3
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x float> poison, float 3.0, i32 0
+ %splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
+ %bo = fmul <vscale x 4 x float> %x, %splat
+ %ext = extractelement <vscale x 4 x float> %bo, i32 3
+ ret float %ext
+}
+
+define float @extractelt_fdiv_nxv4f32_splat(<vscale x 4 x float> %x) {
+; CHECK-LABEL: extractelt_fdiv_nxv4f32_splat:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, %hi(.LCPI48_0)
+; CHECK-NEXT: flw ft0, %lo(.LCPI48_0)(a0)
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT: vfdiv.vf v8, v8, ft0
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x float> poison, float 3.0, i32 0
+ %splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
+ %bo = fdiv <vscale x 4 x float> %x, %splat
+ %ext = extractelement <vscale x 4 x float> %bo, i32 0
+ ret float %ext
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll
index 7f805723f7fe..3cc57f2aab61 100644
--- a/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll
@@ -510,3 +510,73 @@ define void @store_vfmv_f_s_nxv8f64(<vscale x 8 x double>* %x, double* %p) {
}
declare double @llvm.riscv.vfmv.f.s.nxv8f64(<vscale x 8 x double>)
+
+define float @extractelt_fadd_nxv4f32_splat(<vscale x 4 x float> %x) {
+; CHECK-LABEL: extractelt_fadd_nxv4f32_splat:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, %hi(.LCPI47_0)
+; CHECK-NEXT: flw ft0, %lo(.LCPI47_0)(a0)
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT: vfadd.vf v8, v8, ft0
+; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x float> poison, float 3.0, i32 0
+ %splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
+ %bo = fadd <vscale x 4 x float> %x, %splat
+ %ext = extractelement <vscale x 4 x float> %bo, i32 2
+ ret float %ext
+}
+
+define float @extractelt_fsub_nxv4f32_splat(<vscale x 4 x float> %x) {
+; CHECK-LABEL: extractelt_fsub_nxv4f32_splat:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, %hi(.LCPI48_0)
+; CHECK-NEXT: flw ft0, %lo(.LCPI48_0)(a0)
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT: vfrsub.vf v8, v8, ft0
+; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
+; CHECK-NEXT: vslidedown.vi v8, v8, 1
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x float> poison, float 3.0, i32 0
+ %splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
+ %bo = fsub <vscale x 4 x float> %splat, %x
+ %ext = extractelement <vscale x 4 x float> %bo, i32 1
+ ret float %ext
+}
+
+define float @extractelt_fmul_nxv4f32_splat(<vscale x 4 x float> %x) {
+; CHECK-LABEL: extractelt_fmul_nxv4f32_splat:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, %hi(.LCPI49_0)
+; CHECK-NEXT: flw ft0, %lo(.LCPI49_0)(a0)
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT: vfmul.vf v8, v8, ft0
+; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
+; CHECK-NEXT: vslidedown.vi v8, v8, 3
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x float> poison, float 3.0, i32 0
+ %splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
+ %bo = fmul <vscale x 4 x float> %x, %splat
+ %ext = extractelement <vscale x 4 x float> %bo, i32 3
+ ret float %ext
+}
+
+define float @extractelt_fdiv_nxv4f32_splat(<vscale x 4 x float> %x) {
+; CHECK-LABEL: extractelt_fdiv_nxv4f32_splat:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, %hi(.LCPI50_0)
+; CHECK-NEXT: flw ft0, %lo(.LCPI50_0)(a0)
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT: vfdiv.vf v8, v8, ft0
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x float> poison, float 3.0, i32 0
+ %splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
+ %bo = fdiv <vscale x 4 x float> %x, %splat
+ %ext = extractelement <vscale x 4 x float> %bo, i32 0
+ ret float %ext
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
index 9ba3f863c0cc..9486f1c5100f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
@@ -741,3 +741,88 @@ define i64 @extractelt_nxv8i64_idx(<vscale x 8 x i64> %v, i32 %idx) {
%r = extractelement <vscale x 8 x i64> %v, i32 %idx
ret i64 %r
}
+
+define i32 @extractelt_add_nxv4i32_splat(<vscale x 4 x i32> %x) {
+; CHECK-LABEL: extractelt_add_nxv4i32_splat:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT: vadd.vi v8, v8, 3
+; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
+ %bo = add <vscale x 4 x i32> %x, %splat
+ %ext = extractelement <vscale x 4 x i32> %bo, i32 2
+ ret i32 %ext
+}
+
+define i32 @extractelt_sub_nxv4i32_splat(<vscale x 4 x i32> %x) {
+; CHECK-LABEL: extractelt_sub_nxv4i32_splat:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT: vrsub.vi v8, v8, 3
+; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
+; CHECK-NEXT: vslidedown.vi v8, v8, 1
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
+ %bo = sub <vscale x 4 x i32> %splat, %x
+ %ext = extractelement <vscale x 4 x i32> %bo, i32 1
+ ret i32 %ext
+}
+
+define i32 @extractelt_mul_nxv4i32_splat(<vscale x 4 x i32> %x) {
+; CHECK-LABEL: extractelt_mul_nxv4i32_splat:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a0, 3
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT: vmul.vx v8, v8, a0
+; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
+; CHECK-NEXT: vslidedown.vi v8, v8, 3
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
+ %bo = mul <vscale x 4 x i32> %x, %splat
+ %ext = extractelement <vscale x 4 x i32> %bo, i32 3
+ ret i32 %ext
+}
+
+define i32 @extractelt_sdiv_nxv4i32_splat(<vscale x 4 x i32> %x) {
+; CHECK-LABEL: extractelt_sdiv_nxv4i32_splat:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 349525
+; CHECK-NEXT: addi a0, a0, 1366
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT: vmulh.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v10, v8, 31
+; CHECK-NEXT: vadd.vv v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
+ %bo = sdiv <vscale x 4 x i32> %x, %splat
+ %ext = extractelement <vscale x 4 x i32> %bo, i32 0
+ ret i32 %ext
+}
+
+define i32 @extractelt_udiv_nxv4i32_splat(<vscale x 4 x i32> %x) {
+; CHECK-LABEL: extractelt_udiv_nxv4i32_splat:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 349525
+; CHECK-NEXT: addi a0, a0, 1366
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT: vmulh.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v10, v8, 31
+; CHECK-NEXT: vadd.vv v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
+ %bo = sdiv <vscale x 4 x i32> %x, %splat
+ %ext = extractelement <vscale x 4 x i32> %bo, i32 0
+ ret i32 %ext
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
index ac8b4cd56316..85a99dbbd4ab 100644
--- a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
@@ -705,3 +705,88 @@ define i64 @extractelt_nxv8i64_idx(<vscale x 8 x i64> %v, i32 signext %idx) {
%r = extractelement <vscale x 8 x i64> %v, i32 %idx
ret i64 %r
}
+
+define i32 @extractelt_add_nxv4i32_splat(<vscale x 4 x i32> %x) {
+; CHECK-LABEL: extractelt_add_nxv4i32_splat:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT: vadd.vi v8, v8, 3
+; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
+ %bo = add <vscale x 4 x i32> %x, %splat
+ %ext = extractelement <vscale x 4 x i32> %bo, i32 2
+ ret i32 %ext
+}
+
+define i32 @extractelt_sub_nxv4i32_splat(<vscale x 4 x i32> %x) {
+; CHECK-LABEL: extractelt_sub_nxv4i32_splat:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT: vrsub.vi v8, v8, 3
+; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
+; CHECK-NEXT: vslidedown.vi v8, v8, 1
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
+ %bo = sub <vscale x 4 x i32> %splat, %x
+ %ext = extractelement <vscale x 4 x i32> %bo, i32 1
+ ret i32 %ext
+}
+
+define i32 @extractelt_mul_nxv4i32_splat(<vscale x 4 x i32> %x) {
+; CHECK-LABEL: extractelt_mul_nxv4i32_splat:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a0, 3
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT: vmul.vx v8, v8, a0
+; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, mu
+; CHECK-NEXT: vslidedown.vi v8, v8, 3
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
+ %bo = mul <vscale x 4 x i32> %x, %splat
+ %ext = extractelement <vscale x 4 x i32> %bo, i32 3
+ ret i32 %ext
+}
+
+define i32 @extractelt_sdiv_nxv4i32_splat(<vscale x 4 x i32> %x) {
+; CHECK-LABEL: extractelt_sdiv_nxv4i32_splat:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 349525
+; CHECK-NEXT: addiw a0, a0, 1366
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT: vmulh.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v10, v8, 31
+; CHECK-NEXT: vadd.vv v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
+ %bo = sdiv <vscale x 4 x i32> %x, %splat
+ %ext = extractelement <vscale x 4 x i32> %bo, i32 0
+ ret i32 %ext
+}
+
+define i32 @extractelt_udiv_nxv4i32_splat(<vscale x 4 x i32> %x) {
+; CHECK-LABEL: extractelt_udiv_nxv4i32_splat:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 349525
+; CHECK-NEXT: addiw a0, a0, 1366
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT: vmulh.vx v8, v8, a0
+; CHECK-NEXT: vsrl.vi v10, v8, 31
+; CHECK-NEXT: vadd.vv v8, v8, v10
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> poison, i32 3, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
+ %bo = sdiv <vscale x 4 x i32> %x, %splat
+ %ext = extractelement <vscale x 4 x i32> %bo, i32 0
+ ret i32 %ext
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
index 380b9c0f7882..18df0ef51306 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
@@ -611,3 +611,192 @@ define void @store_extractelt_v2f64(<2 x double>* %x, double* %p) nounwind {
store double %b, double* %p
ret void
}
+
+define i32 @extractelt_add_v4i32(<4 x i32> %x) {
+; CHECK-LABEL: extractelt_add_v4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; CHECK-NEXT: vadd.vi v8, v8, 13
+; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %bo = add <4 x i32> %x, <i32 11, i32 12, i32 13, i32 14>
+ %ext = extractelement <4 x i32> %bo, i32 2
+ ret i32 %ext
+}
+
+define i32 @extractelt_sub_v4i32(<4 x i32> %x) {
+; CHECK-LABEL: extractelt_sub_v4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; CHECK-NEXT: vrsub.vi v8, v8, 13
+; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %bo = sub <4 x i32> <i32 11, i32 12, i32 13, i32 14>, %x
+ %ext = extractelement <4 x i32> %bo, i32 2
+ ret i32 %ext
+}
+
+define i32 @extractelt_mul_v4i32(<4 x i32> %x) {
+; CHECK-LABEL: extractelt_mul_v4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a0, 13
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; CHECK-NEXT: vmul.vx v8, v8, a0
+; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %bo = mul <4 x i32> %x, <i32 11, i32 12, i32 13, i32 14>
+ %ext = extractelement <4 x i32> %bo, i32 2
+ ret i32 %ext
+}
+
+define i32 @extractelt_sdiv_v4i32(<4 x i32> %x) {
+; RV32-LABEL: extractelt_sdiv_v4i32:
+; RV32: # %bb.0:
+; RV32-NEXT: li a0, -1
+; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; RV32-NEXT: vmv.s.x v9, a0
+; RV32-NEXT: vmv.v.i v10, 0
+; RV32-NEXT: vsetvli zero, zero, e32, m1, tu, mu
+; RV32-NEXT: vslideup.vi v10, v9, 3
+; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; RV32-NEXT: lui a0, %hi(.LCPI38_0)
+; RV32-NEXT: addi a0, a0, %lo(.LCPI38_0)
+; RV32-NEXT: vle32.v v9, (a0)
+; RV32-NEXT: lui a0, %hi(.LCPI38_1)
+; RV32-NEXT: addi a0, a0, %lo(.LCPI38_1)
+; RV32-NEXT: vle32.v v11, (a0)
+; RV32-NEXT: vand.vv v10, v8, v10
+; RV32-NEXT: vmulh.vv v8, v8, v9
+; RV32-NEXT: vadd.vv v8, v8, v10
+; RV32-NEXT: vsra.vv v9, v8, v11
+; RV32-NEXT: vsrl.vi v8, v8, 31
+; RV32-NEXT: vadd.vv v8, v9, v8
+; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, mu
+; RV32-NEXT: vslidedown.vi v8, v8, 2
+; RV32-NEXT: vmv.x.s a0, v8
+; RV32-NEXT: ret
+;
+; RV64-LABEL: extractelt_sdiv_v4i32:
+; RV64: # %bb.0:
+; RV64-NEXT: li a0, -1
+; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; RV64-NEXT: vmv.s.x v9, a0
+; RV64-NEXT: vmv.v.i v10, 0
+; RV64-NEXT: vsetvli zero, zero, e32, m1, tu, mu
+; RV64-NEXT: vslideup.vi v10, v9, 3
+; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; RV64-NEXT: lui a0, %hi(.LCPI38_0)
+; RV64-NEXT: addi a0, a0, %lo(.LCPI38_0)
+; RV64-NEXT: vle32.v v9, (a0)
+; RV64-NEXT: lui a0, %hi(.LCPI38_1)
+; RV64-NEXT: addi a0, a0, %lo(.LCPI38_1)
+; RV64-NEXT: vle32.v v11, (a0)
+; RV64-NEXT: vand.vv v10, v8, v10
+; RV64-NEXT: vmulh.vv v8, v8, v9
+; RV64-NEXT: vadd.vv v8, v8, v10
+; RV64-NEXT: vsra.vv v8, v8, v11
+; RV64-NEXT: vsrl.vi v9, v8, 31
+; RV64-NEXT: vadd.vv v8, v8, v9
+; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, mu
+; RV64-NEXT: vslidedown.vi v8, v8, 2
+; RV64-NEXT: vmv.x.s a0, v8
+; RV64-NEXT: ret
+ %bo = sdiv <4 x i32> %x, <i32 11, i32 12, i32 13, i32 14>
+ %ext = extractelement <4 x i32> %bo, i32 2
+ ret i32 %ext
+}
+
+define i32 @extractelt_udiv_v4i32(<4 x i32> %x) {
+; CHECK-LABEL: extractelt_udiv_v4i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a0, 1
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; CHECK-NEXT: vmv.s.x v9, a0
+; CHECK-NEXT: vmv.v.i v10, 0
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, mu
+; CHECK-NEXT: vslideup.vi v10, v9, 3
+; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
+; CHECK-NEXT: lui a0, %hi(.LCPI39_0)
+; CHECK-NEXT: addi a0, a0, %lo(.LCPI39_0)
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: vsrl.vv v8, v8, v10
+; CHECK-NEXT: vmulhu.vv v8, v8, v9
+; CHECK-NEXT: vsrl.vi v8, v8, 2
+; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vmv.x.s a0, v8
+; CHECK-NEXT: ret
+ %bo = udiv <4 x i32> %x, <i32 11, i32 12, i32 13, i32 14>
+ %ext = extractelement <4 x i32> %bo, i32 2
+ ret i32 %ext
+}
+
+define float @extractelt_fadd_v4f32(<4 x float> %x) {
+; CHECK-LABEL: extractelt_fadd_v4f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, %hi(.LCPI40_0)
+; CHECK-NEXT: flw ft0, %lo(.LCPI40_0)(a0)
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; CHECK-NEXT: vfadd.vf v8, v8, ft0
+; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %bo = fadd <4 x float> %x, <float 11.0, float 12.0, float 13.0, float 14.0>
+ %ext = extractelement <4 x float> %bo, i32 2
+ ret float %ext
+}
+
+define float @extractelt_fsub_v4f32(<4 x float> %x) {
+; CHECK-LABEL: extractelt_fsub_v4f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, %hi(.LCPI41_0)
+; CHECK-NEXT: flw ft0, %lo(.LCPI41_0)(a0)
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; CHECK-NEXT: vfrsub.vf v8, v8, ft0
+; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %bo = fsub <4 x float> <float 11.0, float 12.0, float 13.0, float 14.0>, %x
+ %ext = extractelement <4 x float> %bo, i32 2
+ ret float %ext
+}
+
+define float @extractelt_fmul_v4f32(<4 x float> %x) {
+; CHECK-LABEL: extractelt_fmul_v4f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, %hi(.LCPI42_0)
+; CHECK-NEXT: flw ft0, %lo(.LCPI42_0)(a0)
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; CHECK-NEXT: vfmul.vf v8, v8, ft0
+; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %bo = fmul <4 x float> %x, <float 11.0, float 12.0, float 13.0, float 14.0>
+ %ext = extractelement <4 x float> %bo, i32 2
+ ret float %ext
+}
+
+define float @extractelt_fdiv_v4f32(<4 x float> %x) {
+; CHECK-LABEL: extractelt_fdiv_v4f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, %hi(.LCPI43_0)
+; CHECK-NEXT: flw ft0, %lo(.LCPI43_0)(a0)
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
+; CHECK-NEXT: vfdiv.vf v8, v8, ft0
+; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, mu
+; CHECK-NEXT: vslidedown.vi v8, v8, 2
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %bo = fdiv <4 x float> %x, <float 11.0, float 12.0, float 13.0, float 14.0>
+ %ext = extractelement <4 x float> %bo, i32 2
+ ret float %ext
+}
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