[PATCH] D129150: [DAG] Canonicalize non-inlane shuffle -> AND if all non-inlane referenced elements are known zero (WIP)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: llvm/test/CodeGen/X86/vselect-constants.ll:304
 ; AVX-NEXT:    vpsraw $15, %xmm0, %xmm0
+; AVX-NEXT:    vmovdqa {{.*#+}} xmm1 = [1,0,0,0]
 ; AVX-NEXT:    vpblendvb %xmm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
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deadalnix wrote:
> Do you know what's up with this guy? This seems objectively worse.
We currently reuse the <1,0,0,0> vector constant, purely by chance not design. Anything that attempts to exploit the zero bits tends to break that lucky pattern.

Whats the real annoyance is that the <1,0,0,0> was originally <i1 true, i1 false>, but we zero-extended it to <i64 1, i64 0> during promotion instead of sign-extending it which made it a lot harder to fold with the 'all sign bits' elements from the compare - with a little luck this would have folded away entirely as part of shuffle combining :-( 


Repository:
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  https://reviews.llvm.org/D129150/new/

https://reviews.llvm.org/D129150