[PATCH] D121833: [SelectionDAG][RISCV][AMDGPU][ARM] Improve SimplifyDemandedBits for SHL with variable shift amount.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1740
+            Flags.setNoUnsignedWrap(false);
+            SDValue NewOp =
+                TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1, Flags);
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Having reviewed what happens on the RISCV test cases for dropping poison, I think this can be simplified both here and in ISD::ADD/SUB/MUL. I've posted D129511 for that simplification. If it's accepted I'll apply it here too.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121833/new/

https://reviews.llvm.org/D121833