[llvm] 74c9030 - [AArch64] Move fp16 intrinsics tests to new file. NFC

[David Green via llvm-commits]

Author: David Green
Date: 2022-07-11T20:36:46+01:00
New Revision: 74c9030a115d1f847a0e9425749e354a4773fef5

URL: https://github.com/llvm/llvm-project/commit/74c9030a115d1f847a0e9425749e354a4773fef5
DIFF: https://github.com/llvm/llvm-project/commit/74c9030a115d1f847a0e9425749e354a4773fef5.diff

LOG: [AArch64] Move fp16 intrinsics tests to new file. NFC

The enabled features for the existing test do not always include FP16,
which is required for the intrinsics.

Added: 
    llvm/test/CodeGen/AArch64/f16-neon-intrinsics.ll

Modified: 
    llvm/test/CodeGen/AArch64/f16-instructions.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AArch64/f16-instructions.ll b/llvm/test/CodeGen/AArch64/f16-instructions.ll
index f50f566703a78..dc63b5139ca3a 100644
--- a/llvm/test/CodeGen/AArch64/f16-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/f16-instructions.ll
@@ -789,9 +789,6 @@ declare half @llvm.nearbyint.f16(half %a) #0
 declare half @llvm.round.f16(half %a) #0
 declare half @llvm.roundeven.f16(half %a) #0
 declare half @llvm.fmuladd.f16(half %a, half %b, half %c) #0
-declare half @llvm.aarch64.neon.frecpe.f16(half %a) #0
-declare half @llvm.aarch64.neon.frecpx.f16(half %a) #0
-declare half @llvm.aarch64.neon.frsqrte.f16(half %a) #0
 
 ; FALLBACK-NOT: remark:{{.*}}test_sqrt
 ; FALLBACK-FP16-NOT: remark:{{.*}}test_sqrt
@@ -1351,31 +1348,4 @@ define half @test_fmuladd(half %a, half %b, half %c) #0 {
   ret half %r
 }
 
-; CHECK-FP16-LABEL: test_vrecpeh_f16:
-; CHECK-FP16-NEXT: frecpe h0, h0
-; CHECK-FP16-NEXT: ret
-
-define half @test_vrecpeh_f16(half %a) #0 {
-  %r = call half @llvm.aarch64.neon.frecpe.f16(half %a)
-  ret half %r
-}
-
-; CHECK-FP16-LABEL: test_vrecpxh_f16:
-; CHECK-FP16-NEXT: frecpx h0, h0
-; CHECK-FP16-NEXT: ret
-
-define half @test_vrecpxh_f16(half %a) #0 {
-  %r = call half @llvm.aarch64.neon.frecpx.f16(half %a)
-  ret half %r
-}
-
-; CHECK-FP16-LABEL: test_vrsqrteh_f16:
-; CHECK-FP16-NEXT: frsqrte h0, h0
-; CHECK-FP16-NEXT: ret
-
-define half @test_vrsqrteh_f16(half %a) #0 {
-  %r = call half @llvm.aarch64.neon.frsqrte.f16(half %a)
-  ret half %r
-}
-
 attributes #0 = { nounwind }

diff  --git a/llvm/test/CodeGen/AArch64/f16-neon-intrinsics.ll b/llvm/test/CodeGen/AArch64/f16-neon-intrinsics.ll
new file mode 100644
index 0000000000000..69b965eaeabb5
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/f16-neon-intrinsics.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fullfp16 | FileCheck %s
+
+define half @test_vrecpeh_f16(half %a) #0 {
+; CHECK-LABEL: test_vrecpeh_f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    frecpe h0, h0
+; CHECK-NEXT:    ret
+  %r = call half @llvm.aarch64.neon.frecpe.f16(half %a)
+  ret half %r
+}
+
+define half @test_vrecpxh_f16(half %a) #0 {
+; CHECK-LABEL: test_vrecpxh_f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    frecpx h0, h0
+; CHECK-NEXT:    ret
+  %r = call half @llvm.aarch64.neon.frecpx.f16(half %a)
+  ret half %r
+}
+
+define half @test_vrsqrteh_f16(half %a) #0 {
+; CHECK-LABEL: test_vrsqrteh_f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    frsqrte h0, h0
+; CHECK-NEXT:    ret
+  %r = call half @llvm.aarch64.neon.frsqrte.f16(half %a)
+  ret half %r
+}
+
+declare half @llvm.aarch64.neon.frecpe.f16(half %a) #0
+declare half @llvm.aarch64.neon.frecpx.f16(half %a) #0
+declare half @llvm.aarch64.neon.frsqrte.f16(half %a) #0