[llvm] ca13555 - [RISCV] Pre-commit tests for D121833. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-07-11T12:14:29-07:00
New Revision: ca13555e0c2c4d271e6a1b5ded4d208b8dfcbb34

URL: https://github.com/llvm/llvm-project/commit/ca13555e0c2c4d271e6a1b5ded4d208b8dfcbb34
DIFF: https://github.com/llvm/llvm-project/commit/ca13555e0c2c4d271e6a1b5ded4d208b8dfcbb34.diff

LOG: [RISCV] Pre-commit tests for D121833. NFC

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/alu16.ll
    llvm/test/CodeGen/RISCV/alu8.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/alu16.ll b/llvm/test/CodeGen/RISCV/alu16.ll
index a46af2053ae03..ef9726fe28d68 100644
--- a/llvm/test/CodeGen/RISCV/alu16.ll
+++ b/llvm/test/CodeGen/RISCV/alu16.ll
@@ -209,6 +209,55 @@ define i16 @sll(i16 %a, i16 %b) nounwind {
   ret i16 %1
 }
 
+; Test the pattern we get from C integer promotion.
+define void @sll_ext(i16 %a, i32 signext %b, i16* %p) nounwind {
+; RV32I-LABEL: sll_ext:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    slli a0, a0, 16
+; RV32I-NEXT:    srli a0, a0, 16
+; RV32I-NEXT:    sll a0, a0, a1
+; RV32I-NEXT:    sh a0, 0(a2)
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: sll_ext:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a0, a0, 48
+; RV64I-NEXT:    srli a0, a0, 48
+; RV64I-NEXT:    sllw a0, a0, a1
+; RV64I-NEXT:    sh a0, 0(a2)
+; RV64I-NEXT:    ret
+  %1 = zext i16 %a to i32
+  %2 = shl i32 %1, %b
+  %3 = trunc i32 %2 to i16
+  store i16 %3, i16* %p
+  ret void
+}
+
+; Test the pattern we get from C integer promotion. This time with poison
+; generating flags.
+define void @sll_ext_drop_poison(i16 %a, i32 signext %b, i16* %p) nounwind {
+; RV32I-LABEL: sll_ext_drop_poison:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    slli a0, a0, 16
+; RV32I-NEXT:    srli a0, a0, 16
+; RV32I-NEXT:    sll a0, a0, a1
+; RV32I-NEXT:    sh a0, 0(a2)
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: sll_ext_drop_poison:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a0, a0, 48
+; RV64I-NEXT:    srli a0, a0, 48
+; RV64I-NEXT:    sllw a0, a0, a1
+; RV64I-NEXT:    sh a0, 0(a2)
+; RV64I-NEXT:    ret
+  %1 = zext i16 %a to i32
+  %2 = shl nuw nsw i32 %1, %b
+  %3 = trunc i32 %2 to i16
+  store i16 %3, i16* %p
+  ret void
+}
+
 define i16 @slt(i16 %a, i16 %b) nounwind {
 ; RV32I-LABEL: slt:
 ; RV32I:       # %bb.0:

diff  --git a/llvm/test/CodeGen/RISCV/alu8.ll b/llvm/test/CodeGen/RISCV/alu8.ll
index dafa328450d9d..52a843ad7b3fa 100644
--- a/llvm/test/CodeGen/RISCV/alu8.ll
+++ b/llvm/test/CodeGen/RISCV/alu8.ll
@@ -207,6 +207,51 @@ define i8 @sll(i8 %a, i8 %b) nounwind {
   ret i8 %1
 }
 
+; Test the pattern we get from C integer promotion.
+define void @sll_ext(i8 %a, i32 signext %b, i8* %p) nounwind {
+; RV32I-LABEL: sll_ext:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    andi a0, a0, 255
+; RV32I-NEXT:    sll a0, a0, a1
+; RV32I-NEXT:    sb a0, 0(a2)
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: sll_ext:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    andi a0, a0, 255
+; RV64I-NEXT:    sllw a0, a0, a1
+; RV64I-NEXT:    sb a0, 0(a2)
+; RV64I-NEXT:    ret
+  %1 = zext i8 %a to i32
+  %2 = shl i32 %1, %b
+  %3 = trunc i32 %2 to i8
+  store i8 %3, i8* %p
+  ret void
+}
+
+; Test the pattern we get from C integer promotion. This time with poison
+; generating flags.
+define void @sll_ext_drop_poison(i8 %a, i32 signext %b, i8* %p) nounwind {
+; RV32I-LABEL: sll_ext_drop_poison:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    andi a0, a0, 255
+; RV32I-NEXT:    sll a0, a0, a1
+; RV32I-NEXT:    sb a0, 0(a2)
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: sll_ext_drop_poison:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    andi a0, a0, 255
+; RV64I-NEXT:    sllw a0, a0, a1
+; RV64I-NEXT:    sb a0, 0(a2)
+; RV64I-NEXT:    ret
+  %1 = zext i8 %a to i32
+  %2 = shl nuw nsw i32 %1, %b
+  %3 = trunc i32 %2 to i8
+  store i8 %3, i8* %p
+  ret void
+}
+
 define i8 @slt(i8 %a, i8 %b) nounwind {
 ; RV32I-LABEL: slt:
 ; RV32I:       # %bb.0: