[PATCH] D121833: [SelectionDAG][RISCV][AMDGPU][ARM] Improve SimplifyDemandedBits for SHL with variable shift amount.

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Jul 11 12:07:12 PDT 2022


craig.topper updated this revision to Diff 443709.
craig.topper added a comment.

Drop poison flags


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121833/new/

https://reviews.llvm.org/D121833

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/AMDGPU/shl.ll
  llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
  llvm/test/CodeGen/RISCV/alu16.ll
  llvm/test/CodeGen/RISCV/alu8.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-loops.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D121833.443709.patch
Type: text/x-patch
Size: 12985 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220711/9e922662/attachment.bin>


More information about the llvm-commits mailing list