[llvm] 4670c1e - [AArch64] add test for possible sub->xor enhancement; NFC

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2022-07-11T12:37:35-04:00
New Revision: 4670c1e55d2411c04dbb2b9a9729a221dbc37c3b

URL: https://github.com/llvm/llvm-project/commit/4670c1e55d2411c04dbb2b9a9729a221dbc37c3b
DIFF: https://github.com/llvm/llvm-project/commit/4670c1e55d2411c04dbb2b9a9729a221dbc37c3b.diff

LOG: [AArch64] add test for possible sub->xor enhancement; NFC

Added: 
    

Modified: 
    llvm/test/CodeGen/AArch64/sub1.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AArch64/sub1.ll b/llvm/test/CodeGen/AArch64/sub1.ll
index 97dafcd699228..611426e1d6b86 100644
--- a/llvm/test/CodeGen/AArch64/sub1.ll
+++ b/llvm/test/CodeGen/AArch64/sub1.ll
@@ -26,6 +26,21 @@ define i8 @masked_sub_i8(i8 %x) {
   ret i8 %m
 }
 
+; TODO: Borrow from the MSB is ok.
+
+define i8 @masked_sub_high_bit_mask_i8(i8 %x) {
+; CHECK-LABEL: masked_sub_high_bit_mask_i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #-96
+; CHECK-NEXT:    mov w9, #60
+; CHECK-NEXT:    and w8, w0, w8
+; CHECK-NEXT:    sub w0, w9, w8
+; CHECK-NEXT:    ret
+  %maskx = and i8 %x, 160 ; 0b10100000
+  %s = sub i8 60, %maskx  ; 0b00111100
+  ret i8 %s
+}
+
 define i8 @not_masked_sub_i8(i8 %x) {
 ; CHECK-LABEL: not_masked_sub_i8:
 ; CHECK:       // %bb.0: