[PATCH] D129381: [AMDGPU][CodeGen] Support (register + immediate) SMRD offsets.

[Ivan Kosarev via Phabricator via llvm-commits]

kosarev added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/amdgcn-load-offset-from-reg.ll:1-2
-; RUN: llc -march=amdgcn -global-isel=0 -verify-machineinstrs -stop-after=amdgpu-isel -o - %s | FileCheck -check-prefixes=GCN,SDAG %s
-; RUN: llc -march=amdgcn -global-isel=1 -verify-machineinstrs -stop-after=amdgpu-isel -o - %s | FileCheck -check-prefixes=GCN,GISEL %s
+; RUN: llc -march=amdgcn -mcpu=gfx900 -global-isel=0 -verify-machineinstrs -stop-after=amdgpu-isel -o - %s | FileCheck -check-prefixes=GCN,SDAG %s
+; RUN: llc -march=amdgcn -mcpu=gfx900 -global-isel=1 -verify-machineinstrs -stop-after=amdgpu-isel -o - %s | FileCheck -check-prefixes=GCN,GISEL %s
 
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arsenm wrote:
> You shouldn't use -stop-after=amdgpu-isel. Use finalize-isel for MIR tests (although I'm not sure why you're testing MIR here)
This seems to be where we already have checks for a similar case? Is there a better place for that?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D129381/new/

https://reviews.llvm.org/D129381