[llvm] 0a11ad2 - [ARM] Expand MVE i1 fptoint and inttofp if mve.fp is not present.
David Green via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 11 05:03:37 PDT 2022
Author: David Green
Date: 2022-07-11T13:03:30+01:00
New Revision: 0a11ad2aa86aa6c7a0d4ac54099738f4206fa954
URL: https://github.com/llvm/llvm-project/commit/0a11ad2aa86aa6c7a0d4ac54099738f4206fa954
DIFF: https://github.com/llvm/llvm-project/commit/0a11ad2aa86aa6c7a0d4ac54099738f4206fa954.diff
LOG: [ARM] Expand MVE i1 fptoint and inttofp if mve.fp is not present.
If MVE.fp is not present then we cannot select the vector i1 fp
operations to VCMP instructions, so need to expand.
Added:
Modified:
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/test/Analysis/CostModel/ARM/fptoi_sat.ll
llvm/test/CodeGen/Thumb2/mve-pred-ext.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 85e32c08c74cf..b16e0d94bf98c 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -450,6 +450,14 @@ void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
setOperationAction(ISD::TRUNCATE, VT, Custom);
setOperationAction(ISD::VSELECT, VT, Expand);
setOperationAction(ISD::SELECT, VT, Expand);
+ setOperationAction(ISD::SELECT_CC, VT, Expand);
+
+ if (!HasMVEFP) {
+ setOperationAction(ISD::SINT_TO_FP, VT, Expand);
+ setOperationAction(ISD::UINT_TO_FP, VT, Expand);
+ setOperationAction(ISD::FP_TO_SINT, VT, Expand);
+ setOperationAction(ISD::FP_TO_UINT, VT, Expand);
+ }
}
setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
setOperationAction(ISD::TRUNCATE, MVT::v2i1, Expand);
diff --git a/llvm/test/Analysis/CostModel/ARM/fptoi_sat.ll b/llvm/test/Analysis/CostModel/ARM/fptoi_sat.ll
index cfa8554a6d81a..c6d8946eb0782 100644
--- a/llvm/test/Analysis/CostModel/ARM/fptoi_sat.ll
+++ b/llvm/test/Analysis/CostModel/ARM/fptoi_sat.ll
@@ -44,8 +44,8 @@ define void @casts() {
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 88 for instruction: %v2f64u32 = call <2 x i32> @llvm.fptoui.sat.v2i32.v2f64(<2 x double> undef)
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 134 for instruction: %v2f64s64 = call <2 x i64> @llvm.fptosi.sat.v2i64.v2f64(<2 x double> undef)
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 120 for instruction: %v2f64u64 = call <2 x i64> @llvm.fptoui.sat.v2i64.v2f64(<2 x double> undef)
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 170 for instruction: %v4f32s1 = call <4 x i1> @llvm.fptosi.sat.v4i1.v4f32(<4 x float> undef)
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 106 for instruction: %v4f32u1 = call <4 x i1> @llvm.fptoui.sat.v4i1.v4f32(<4 x float> undef)
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 240 for instruction: %v4f32s1 = call <4 x i1> @llvm.fptosi.sat.v4i1.v4f32(<4 x float> undef)
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 176 for instruction: %v4f32u1 = call <4 x i1> @llvm.fptoui.sat.v4i1.v4f32(<4 x float> undef)
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 202 for instruction: %v4f32s8 = call <4 x i8> @llvm.fptosi.sat.v4i8.v4f32(<4 x float> undef)
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 176 for instruction: %v4f32u8 = call <4 x i8> @llvm.fptoui.sat.v4i8.v4f32(<4 x float> undef)
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 202 for instruction: %v4f32s16 = call <4 x i16> @llvm.fptosi.sat.v4i16.v4f32(<4 x float> undef)
@@ -64,8 +64,8 @@ define void @casts() {
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 250 for instruction: %v4f64u32 = call <4 x i32> @llvm.fptoui.sat.v4i32.v4f64(<4 x double> undef)
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 404 for instruction: %v4f64s64 = call <4 x i64> @llvm.fptosi.sat.v4i64.v4f64(<4 x double> undef)
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 376 for instruction: %v4f64u64 = call <4 x i64> @llvm.fptoui.sat.v4i64.v4f64(<4 x double> undef)
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 346 for instruction: %v8f32s1 = call <8 x i1> @llvm.fptosi.sat.v8i1.v8f32(<8 x float> undef)
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 218 for instruction: %v8f32u1 = call <8 x i1> @llvm.fptoui.sat.v8i1.v8f32(<8 x float> undef)
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 626 for instruction: %v8f32s1 = call <8 x i1> @llvm.fptosi.sat.v8i1.v8f32(<8 x float> undef)
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 498 for instruction: %v8f32u1 = call <8 x i1> @llvm.fptoui.sat.v8i1.v8f32(<8 x float> undef)
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 548 for instruction: %v8f32s8 = call <8 x i8> @llvm.fptosi.sat.v8i8.v8f32(<8 x float> undef)
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 498 for instruction: %v8f32u8 = call <8 x i8> @llvm.fptoui.sat.v8i8.v8f32(<8 x float> undef)
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 548 for instruction: %v8f32s16 = call <8 x i16> @llvm.fptosi.sat.v8i16.v8f32(<8 x float> undef)
@@ -84,8 +84,8 @@ define void @casts() {
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 792 for instruction: %v8f64u32 = call <8 x i32> @llvm.fptoui.sat.v8i32.v8f64(<8 x double> undef)
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1352 for instruction: %v8f64s64 = call <8 x i64> @llvm.fptosi.sat.v8i64.v8f64(<8 x double> undef)
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1296 for instruction: %v8f64u64 = call <8 x i64> @llvm.fptoui.sat.v8i64.v8f64(<8 x double> undef)
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 714 for instruction: %v16f32s1 = call <16 x i1> @llvm.fptosi.sat.v16i1.v16f32(<16 x float> undef)
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 458 for instruction: %v16f32u1 = call <16 x i1> @llvm.fptoui.sat.v16i1.v16f32(<16 x float> undef)
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1834 for instruction: %v16f32s1 = call <16 x i1> @llvm.fptosi.sat.v16i1.v16f32(<16 x float> undef)
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1578 for instruction: %v16f32u1 = call <16 x i1> @llvm.fptoui.sat.v16i1.v16f32(<16 x float> undef)
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1676 for instruction: %v16f32s8 = call <16 x i8> @llvm.fptosi.sat.v16i8.v16f32(<16 x float> undef)
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1578 for instruction: %v16f32u8 = call <16 x i8> @llvm.fptoui.sat.v16i8.v16f32(<16 x float> undef)
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1676 for instruction: %v16f32s16 = call <16 x i16> @llvm.fptosi.sat.v16i16.v16f32(<16 x float> undef)
@@ -344,8 +344,8 @@ define void @fp16() {
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 88 for instruction: %v2f16u32 = call <2 x i32> @llvm.fptoui.sat.v2i32.v2f16(<2 x half> undef)
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 134 for instruction: %v2f16s64 = call <2 x i64> @llvm.fptosi.sat.v2i64.v2f16(<2 x half> undef)
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 120 for instruction: %v2f16u64 = call <2 x i64> @llvm.fptoui.sat.v2i64.v2f16(<2 x half> undef)
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 170 for instruction: %v4f16s1 = call <4 x i1> @llvm.fptosi.sat.v4i1.v4f16(<4 x half> undef)
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 106 for instruction: %v4f16u1 = call <4 x i1> @llvm.fptoui.sat.v4i1.v4f16(<4 x half> undef)
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 240 for instruction: %v4f16s1 = call <4 x i1> @llvm.fptosi.sat.v4i1.v4f16(<4 x half> undef)
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 176 for instruction: %v4f16u1 = call <4 x i1> @llvm.fptoui.sat.v4i1.v4f16(<4 x half> undef)
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 202 for instruction: %v4f16s8 = call <4 x i8> @llvm.fptosi.sat.v4i8.v4f16(<4 x half> undef)
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 176 for instruction: %v4f16u8 = call <4 x i8> @llvm.fptoui.sat.v4i8.v4f16(<4 x half> undef)
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 202 for instruction: %v4f16s16 = call <4 x i16> @llvm.fptosi.sat.v4i16.v4f16(<4 x half> undef)
@@ -354,8 +354,8 @@ define void @fp16() {
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 176 for instruction: %v4f16u32 = call <4 x i32> @llvm.fptoui.sat.v4i32.v4f16(<4 x half> undef)
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 406 for instruction: %v4f16s64 = call <4 x i64> @llvm.fptosi.sat.v4i64.v4f16(<4 x half> undef)
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 378 for instruction: %v4f16u64 = call <4 x i64> @llvm.fptoui.sat.v4i64.v4f16(<4 x half> undef)
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 338 for instruction: %v8f16s1 = call <8 x i1> @llvm.fptosi.sat.v8i1.v8f16(<8 x half> undef)
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 210 for instruction: %v8f16u1 = call <8 x i1> @llvm.fptoui.sat.v8i1.v8f16(<8 x half> undef)
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 480 for instruction: %v8f16s1 = call <8 x i1> @llvm.fptosi.sat.v8i1.v8f16(<8 x half> undef)
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 352 for instruction: %v8f16u1 = call <8 x i1> @llvm.fptoui.sat.v8i1.v8f16(<8 x half> undef)
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 402 for instruction: %v8f16s8 = call <8 x i8> @llvm.fptosi.sat.v8i8.v8f16(<8 x half> undef)
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 352 for instruction: %v8f16u8 = call <8 x i8> @llvm.fptoui.sat.v8i8.v8f16(<8 x half> undef)
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 402 for instruction: %v8f16s16 = call <8 x i16> @llvm.fptosi.sat.v8i16.v8f16(<8 x half> undef)
@@ -364,8 +364,8 @@ define void @fp16() {
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 498 for instruction: %v8f16u32 = call <8 x i32> @llvm.fptoui.sat.v8i32.v8f16(<8 x half> undef)
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1362 for instruction: %v8f16s64 = call <8 x i64> @llvm.fptosi.sat.v8i64.v8f16(<8 x half> undef)
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1306 for instruction: %v8f16u64 = call <8 x i64> @llvm.fptoui.sat.v8i64.v8f16(<8 x half> undef)
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 682 for instruction: %v16f16s1 = call <16 x i1> @llvm.fptosi.sat.v16i1.v16f16(<16 x half> undef)
-; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 426 for instruction: %v16f16u1 = call <16 x i1> @llvm.fptoui.sat.v16i1.v16f16(<16 x half> undef)
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1250 for instruction: %v16f16s1 = call <16 x i1> @llvm.fptosi.sat.v16i1.v16f16(<16 x half> undef)
+; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 994 for instruction: %v16f16u1 = call <16 x i1> @llvm.fptoui.sat.v16i1.v16f16(<16 x half> undef)
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1092 for instruction: %v16f16s8 = call <16 x i8> @llvm.fptosi.sat.v16i8.v16f16(<16 x half> undef)
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 994 for instruction: %v16f16u8 = call <16 x i8> @llvm.fptoui.sat.v16i8.v16f16(<16 x half> undef)
; CHECK-MVE-NEXT: Cost Model: Found an estimated cost of 1092 for instruction: %v16f16s16 = call <16 x i16> @llvm.fptosi.sat.v16i16.v16f16(<16 x half> undef)
diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-ext.ll b/llvm/test/CodeGen/Thumb2/mve-pred-ext.ll
index ea7a26ee3a9ee..117469f3bd788 100644
--- a/llvm/test/CodeGen/Thumb2/mve-pred-ext.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-pred-ext.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-MVE
+; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-MVEFP
define arm_aapcs_vfpcc <4 x i32> @sext_v4i1_v4i32(<4 x i32> %src) {
; CHECK-LABEL: sext_v4i1_v4i32:
@@ -16,13 +17,31 @@ entry:
}
define arm_aapcs_vfpcc <4 x i32> @sext_v4i1_v4f32(<4 x float> %src1, <4 x float> %src2) {
-; CHECK-LABEL: sext_v4i1_v4f32:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.i32 q2, #0x0
-; CHECK-NEXT: vmov.i8 q3, #0xff
-; CHECK-NEXT: vcmp.f32 ne, q0, q1
-; CHECK-NEXT: vpsel q0, q3, q2
-; CHECK-NEXT: bx lr
+; CHECK-MVE-LABEL: sext_v4i1_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmp.f32 s2, s6
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: csetm r0, ne
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s3, s7
+; CHECK-MVE-NEXT: csetm r1, ne
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s1, s5
+; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
+; CHECK-MVE-NEXT: csetm r2, ne
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: csetm r3, ne
+; CHECK-MVE-NEXT: vmov q0[3], q0[1], r3, r2
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: sext_v4i1_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vmov.i32 q2, #0x0
+; CHECK-MVEFP-NEXT: vmov.i8 q3, #0xff
+; CHECK-MVEFP-NEXT: vcmp.f32 ne, q0, q1
+; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
+; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp une <4 x float> %src1, %src2
%0 = sext <4 x i1> %c to <4 x i32>
@@ -44,13 +63,59 @@ entry:
}
define arm_aapcs_vfpcc <8 x i16> @sext_v8i1_v8f32(<8 x half> %src1, <8 x half> %src2) {
-; CHECK-LABEL: sext_v8i1_v8f32:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.i16 q2, #0x0
-; CHECK-NEXT: vmov.i8 q3, #0xff
-; CHECK-NEXT: vcmp.f16 ne, q0, q1
-; CHECK-NEXT: vpsel q0, q3, q2
-; CHECK-NEXT: bx lr
+; CHECK-MVE-LABEL: sext_v8i1_v8f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .save {r4, r5, r7, lr}
+; CHECK-MVE-NEXT: push {r4, r5, r7, lr}
+; CHECK-MVE-NEXT: vcmp.f16 s3, s7
+; CHECK-MVE-NEXT: vmovx.f16 s8, s7
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vmovx.f16 s10, s3
+; CHECK-MVE-NEXT: vcmp.f16 s10, s8
+; CHECK-MVE-NEXT: csetm r12, ne
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f16 s2, s6
+; CHECK-MVE-NEXT: vmovx.f16 s6, s6
+; CHECK-MVE-NEXT: vmovx.f16 s2, s2
+; CHECK-MVE-NEXT: csetm lr, ne
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f16 s2, s6
+; CHECK-MVE-NEXT: vmovx.f16 s2, s5
+; CHECK-MVE-NEXT: vmovx.f16 s6, s1
+; CHECK-MVE-NEXT: csetm r2, ne
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f16 s1, s5
+; CHECK-MVE-NEXT: csetm r3, ne
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f16 s6, s2
+; CHECK-MVE-NEXT: vmovx.f16 s2, s4
+; CHECK-MVE-NEXT: csetm r0, ne
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f16 s0, s4
+; CHECK-MVE-NEXT: vmovx.f16 s0, s0
+; CHECK-MVE-NEXT: csetm r1, ne
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f16 s0, s2
+; CHECK-MVE-NEXT: csetm r4, ne
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vmov.16 q0[0], r4
+; CHECK-MVE-NEXT: csetm r5, ne
+; CHECK-MVE-NEXT: vmov.16 q0[1], r5
+; CHECK-MVE-NEXT: vmov.16 q0[2], r0
+; CHECK-MVE-NEXT: vmov.16 q0[3], r1
+; CHECK-MVE-NEXT: vmov.16 q0[4], r2
+; CHECK-MVE-NEXT: vmov.16 q0[5], r3
+; CHECK-MVE-NEXT: vmov.16 q0[6], r12
+; CHECK-MVE-NEXT: vmov.16 q0[7], lr
+; CHECK-MVE-NEXT: pop {r4, r5, r7, pc}
+;
+; CHECK-MVEFP-LABEL: sext_v8i1_v8f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vmov.i16 q2, #0x0
+; CHECK-MVEFP-NEXT: vmov.i8 q3, #0xff
+; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, q1
+; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
+; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp une <8 x half> %src1, %src2
%0 = sext <8 x i1> %c to <8 x i16>
@@ -93,37 +158,69 @@ entry:
}
define arm_aapcs_vfpcc <2 x i64> @sext_v2i1_v2f64(<2 x double> %src) {
-; CHECK-LABEL: sext_v2i1_v2f64:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .save {r4, r5, r6, lr}
-; CHECK-NEXT: push {r4, r5, r6, lr}
-; CHECK-NEXT: .vsave {d8, d9}
-; CHECK-NEXT: vpush {d8, d9}
-; CHECK-NEXT: vmov q4, q0
-; CHECK-NEXT: vldr d0, .LCPI6_0
-; CHECK-NEXT: vmov r0, r1, d9
-; CHECK-NEXT: vmov r4, r5, d0
-; CHECK-NEXT: mov r2, r4
-; CHECK-NEXT: mov r3, r5
-; CHECK-NEXT: bl __aeabi_dcmpeq
-; CHECK-NEXT: mov r6, r0
-; CHECK-NEXT: vmov r0, r1, d8
-; CHECK-NEXT: mov r2, r4
-; CHECK-NEXT: mov r3, r5
-; CHECK-NEXT: bl __aeabi_dcmpeq
-; CHECK-NEXT: cmp r6, #0
-; CHECK-NEXT: csetm r1, eq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: csetm r0, eq
-; CHECK-NEXT: vmov q0[2], q0[0], r0, r1
-; CHECK-NEXT: vmov q0[3], q0[1], r0, r1
-; CHECK-NEXT: vpop {d8, d9}
-; CHECK-NEXT: pop {r4, r5, r6, pc}
-; CHECK-NEXT: .p2align 3
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI6_0:
-; CHECK-NEXT: .long 0 @ double 0
-; CHECK-NEXT: .long 0
+; CHECK-MVE-LABEL: sext_v2i1_v2f64:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .save {r4, r5, r6, lr}
+; CHECK-MVE-NEXT: push {r4, r5, r6, lr}
+; CHECK-MVE-NEXT: .vsave {d8, d9}
+; CHECK-MVE-NEXT: vpush {d8, d9}
+; CHECK-MVE-NEXT: vmov q4, q0
+; CHECK-MVE-NEXT: vldr d0, .LCPI6_0
+; CHECK-MVE-NEXT: vmov r0, r1, d9
+; CHECK-MVE-NEXT: vmov r4, r5, d0
+; CHECK-MVE-NEXT: mov r2, r4
+; CHECK-MVE-NEXT: mov r3, r5
+; CHECK-MVE-NEXT: bl __aeabi_dcmpeq
+; CHECK-MVE-NEXT: vmov r2, r1, d8
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: mov r3, r5
+; CHECK-MVE-NEXT: csetm r6, eq
+; CHECK-MVE-NEXT: mov r0, r2
+; CHECK-MVE-NEXT: mov r2, r4
+; CHECK-MVE-NEXT: bl __aeabi_dcmpeq
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: csetm r0, eq
+; CHECK-MVE-NEXT: vmov q0[2], q0[0], r0, r6
+; CHECK-MVE-NEXT: vmov q0[3], q0[1], r0, r6
+; CHECK-MVE-NEXT: vpop {d8, d9}
+; CHECK-MVE-NEXT: pop {r4, r5, r6, pc}
+; CHECK-MVE-NEXT: .p2align 3
+; CHECK-MVE-NEXT: @ %bb.1:
+; CHECK-MVE-NEXT: .LCPI6_0:
+; CHECK-MVE-NEXT: .long 0 @ double 0
+; CHECK-MVE-NEXT: .long 0
+;
+; CHECK-MVEFP-LABEL: sext_v2i1_v2f64:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: .save {r4, r5, r6, lr}
+; CHECK-MVEFP-NEXT: push {r4, r5, r6, lr}
+; CHECK-MVEFP-NEXT: .vsave {d8, d9}
+; CHECK-MVEFP-NEXT: vpush {d8, d9}
+; CHECK-MVEFP-NEXT: vmov q4, q0
+; CHECK-MVEFP-NEXT: vldr d0, .LCPI6_0
+; CHECK-MVEFP-NEXT: vmov r0, r1, d9
+; CHECK-MVEFP-NEXT: vmov r4, r5, d0
+; CHECK-MVEFP-NEXT: mov r2, r4
+; CHECK-MVEFP-NEXT: mov r3, r5
+; CHECK-MVEFP-NEXT: bl __aeabi_dcmpeq
+; CHECK-MVEFP-NEXT: mov r6, r0
+; CHECK-MVEFP-NEXT: vmov r0, r1, d8
+; CHECK-MVEFP-NEXT: mov r2, r4
+; CHECK-MVEFP-NEXT: mov r3, r5
+; CHECK-MVEFP-NEXT: bl __aeabi_dcmpeq
+; CHECK-MVEFP-NEXT: cmp r6, #0
+; CHECK-MVEFP-NEXT: csetm r1, eq
+; CHECK-MVEFP-NEXT: cmp r0, #0
+; CHECK-MVEFP-NEXT: csetm r0, eq
+; CHECK-MVEFP-NEXT: vmov q0[2], q0[0], r0, r1
+; CHECK-MVEFP-NEXT: vmov q0[3], q0[1], r0, r1
+; CHECK-MVEFP-NEXT: vpop {d8, d9}
+; CHECK-MVEFP-NEXT: pop {r4, r5, r6, pc}
+; CHECK-MVEFP-NEXT: .p2align 3
+; CHECK-MVEFP-NEXT: @ %bb.1:
+; CHECK-MVEFP-NEXT: .LCPI6_0:
+; CHECK-MVEFP-NEXT: .long 0 @ double 0
+; CHECK-MVEFP-NEXT: .long 0
entry:
%c = fcmp une <2 x double> %src, zeroinitializer
%0 = sext <2 x i1> %c to <2 x i64>
@@ -146,13 +243,33 @@ entry:
}
define arm_aapcs_vfpcc <4 x i32> @zext_v4i1_v4f32(<4 x float> %src1, <4 x float> %src2) {
-; CHECK-LABEL: zext_v4i1_v4f32:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.i32 q2, #0x0
-; CHECK-NEXT: vmov.i32 q3, #0x1
-; CHECK-NEXT: vcmp.f32 ne, q0, q1
-; CHECK-NEXT: vpsel q0, q3, q2
-; CHECK-NEXT: bx lr
+; CHECK-MVE-LABEL: zext_v4i1_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmp.f32 s3, s7
+; CHECK-MVE-NEXT: vmov.i32 q2, #0x1
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s1, s5
+; CHECK-MVE-NEXT: csetm r0, ne
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s2, s6
+; CHECK-MVE-NEXT: csetm r1, ne
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: csetm r2, ne
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: csetm r3, ne
+; CHECK-MVE-NEXT: vmov q0[2], q0[0], r3, r2
+; CHECK-MVE-NEXT: vmov q0[3], q0[1], r1, r0
+; CHECK-MVE-NEXT: vand q0, q0, q2
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: zext_v4i1_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vmov.i32 q2, #0x0
+; CHECK-MVEFP-NEXT: vmov.i32 q3, #0x1
+; CHECK-MVEFP-NEXT: vcmp.f32 ne, q0, q1
+; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
+; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp une <4 x float> %src1, %src2
%0 = zext <4 x i1> %c to <4 x i32>
@@ -174,13 +291,61 @@ entry:
}
define arm_aapcs_vfpcc <8 x i16> @zext_v8i1_v8f32(<8 x half> %src1, <8 x half> %src2) {
-; CHECK-LABEL: zext_v8i1_v8f32:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.i16 q2, #0x0
-; CHECK-NEXT: vmov.i16 q3, #0x1
-; CHECK-NEXT: vcmp.f16 ne, q0, q1
-; CHECK-NEXT: vpsel q0, q3, q2
-; CHECK-NEXT: bx lr
+; CHECK-MVE-LABEL: zext_v8i1_v8f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .save {r4, r5, r7, lr}
+; CHECK-MVE-NEXT: push {r4, r5, r7, lr}
+; CHECK-MVE-NEXT: vmovx.f16 s8, s7
+; CHECK-MVE-NEXT: vmovx.f16 s10, s3
+; CHECK-MVE-NEXT: vcmp.f16 s10, s8
+; CHECK-MVE-NEXT: vmovx.f16 s8, s6
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vmovx.f16 s10, s2
+; CHECK-MVE-NEXT: vcmp.f16 s10, s8
+; CHECK-MVE-NEXT: vmovx.f16 s8, s5
+; CHECK-MVE-NEXT: vmovx.f16 s10, s1
+; CHECK-MVE-NEXT: csetm r12, ne
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f16 s3, s7
+; CHECK-MVE-NEXT: csetm lr, ne
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f16 s10, s8
+; CHECK-MVE-NEXT: csetm r2, ne
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f16 s2, s6
+; CHECK-MVE-NEXT: vmovx.f16 s2, s4
+; CHECK-MVE-NEXT: vmovx.f16 s6, s0
+; CHECK-MVE-NEXT: csetm r3, ne
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f16 s6, s2
+; CHECK-MVE-NEXT: csetm r0, ne
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f16 s1, s5
+; CHECK-MVE-NEXT: csetm r1, ne
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f16 s0, s4
+; CHECK-MVE-NEXT: vmov.i16 q0, #0x1
+; CHECK-MVE-NEXT: csetm r4, ne
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: csetm r5, ne
+; CHECK-MVE-NEXT: vmov.16 q1[0], r5
+; CHECK-MVE-NEXT: vmov.16 q1[1], r1
+; CHECK-MVE-NEXT: vmov.16 q1[2], r4
+; CHECK-MVE-NEXT: vmov.16 q1[3], r3
+; CHECK-MVE-NEXT: vmov.16 q1[4], r0
+; CHECK-MVE-NEXT: vmov.16 q1[5], lr
+; CHECK-MVE-NEXT: vmov.16 q1[6], r2
+; CHECK-MVE-NEXT: vmov.16 q1[7], r12
+; CHECK-MVE-NEXT: vand q0, q1, q0
+; CHECK-MVE-NEXT: pop {r4, r5, r7, pc}
+;
+; CHECK-MVEFP-LABEL: zext_v8i1_v8f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vmov.i16 q2, #0x0
+; CHECK-MVEFP-NEXT: vmov.i16 q3, #0x1
+; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, q1
+; CHECK-MVEFP-NEXT: vpsel q0, q3, q2
+; CHECK-MVEFP-NEXT: bx lr
entry:
%c = fcmp une <8 x half> %src1, %src2
%0 = zext <8 x i1> %c to <8 x i16>
@@ -229,41 +394,80 @@ entry:
}
define arm_aapcs_vfpcc <2 x i64> @zext_v2i1_v2f64(<2 x double> %src) {
-; CHECK-LABEL: zext_v2i1_v2f64:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .save {r4, r5, r6, lr}
-; CHECK-NEXT: push {r4, r5, r6, lr}
-; CHECK-NEXT: .vsave {d8, d9}
-; CHECK-NEXT: vpush {d8, d9}
-; CHECK-NEXT: vmov q4, q0
-; CHECK-NEXT: vldr d0, .LCPI13_0
-; CHECK-NEXT: vmov r0, r1, d8
-; CHECK-NEXT: vmov r4, r5, d0
-; CHECK-NEXT: mov r2, r4
-; CHECK-NEXT: mov r3, r5
-; CHECK-NEXT: bl __aeabi_dcmpeq
-; CHECK-NEXT: mov r6, r0
-; CHECK-NEXT: vmov r0, r1, d9
-; CHECK-NEXT: mov r2, r4
-; CHECK-NEXT: mov r3, r5
-; CHECK-NEXT: bl __aeabi_dcmpeq
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: vldr s1, .LCPI13_1
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: cmp r6, #0
-; CHECK-NEXT: vmov s2, r0
-; CHECK-NEXT: cset r0, eq
-; CHECK-NEXT: vmov s0, r0
-; CHECK-NEXT: vmov.f32 s3, s1
-; CHECK-NEXT: vpop {d8, d9}
-; CHECK-NEXT: pop {r4, r5, r6, pc}
-; CHECK-NEXT: .p2align 3
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI13_0:
-; CHECK-NEXT: .long 0 @ double 0
-; CHECK-NEXT: .long 0
-; CHECK-NEXT: .LCPI13_1:
-; CHECK-NEXT: .long 0x00000000 @ float 0
+; CHECK-MVE-LABEL: zext_v2i1_v2f64:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: .save {r4, r5, r6, lr}
+; CHECK-MVE-NEXT: push {r4, r5, r6, lr}
+; CHECK-MVE-NEXT: .vsave {d8, d9}
+; CHECK-MVE-NEXT: vpush {d8, d9}
+; CHECK-MVE-NEXT: vmov q4, q0
+; CHECK-MVE-NEXT: vldr d0, .LCPI13_0
+; CHECK-MVE-NEXT: vmov r0, r1, d9
+; CHECK-MVE-NEXT: vmov r4, r5, d0
+; CHECK-MVE-NEXT: mov r2, r4
+; CHECK-MVE-NEXT: mov r3, r5
+; CHECK-MVE-NEXT: bl __aeabi_dcmpeq
+; CHECK-MVE-NEXT: vmov r2, r1, d8
+; CHECK-MVE-NEXT: adr r3, .LCPI13_1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vldrw.u32 q4, [r3]
+; CHECK-MVE-NEXT: mov r3, r5
+; CHECK-MVE-NEXT: csetm r6, eq
+; CHECK-MVE-NEXT: mov r0, r2
+; CHECK-MVE-NEXT: mov r2, r4
+; CHECK-MVE-NEXT: bl __aeabi_dcmpeq
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: csetm r0, eq
+; CHECK-MVE-NEXT: vmov q0[2], q0[0], r0, r6
+; CHECK-MVE-NEXT: vand q0, q0, q4
+; CHECK-MVE-NEXT: vpop {d8, d9}
+; CHECK-MVE-NEXT: pop {r4, r5, r6, pc}
+; CHECK-MVE-NEXT: .p2align 4
+; CHECK-MVE-NEXT: @ %bb.1:
+; CHECK-MVE-NEXT: .LCPI13_1:
+; CHECK-MVE-NEXT: .long 1 @ 0x1
+; CHECK-MVE-NEXT: .long 0 @ 0x0
+; CHECK-MVE-NEXT: .long 1 @ 0x1
+; CHECK-MVE-NEXT: .long 0 @ 0x0
+; CHECK-MVE-NEXT: .LCPI13_0:
+; CHECK-MVE-NEXT: .long 0 @ double 0
+; CHECK-MVE-NEXT: .long 0
+;
+; CHECK-MVEFP-LABEL: zext_v2i1_v2f64:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: .save {r4, r5, r6, lr}
+; CHECK-MVEFP-NEXT: push {r4, r5, r6, lr}
+; CHECK-MVEFP-NEXT: .vsave {d8, d9}
+; CHECK-MVEFP-NEXT: vpush {d8, d9}
+; CHECK-MVEFP-NEXT: vmov q4, q0
+; CHECK-MVEFP-NEXT: vldr d0, .LCPI13_0
+; CHECK-MVEFP-NEXT: vmov r0, r1, d8
+; CHECK-MVEFP-NEXT: vmov r4, r5, d0
+; CHECK-MVEFP-NEXT: mov r2, r4
+; CHECK-MVEFP-NEXT: mov r3, r5
+; CHECK-MVEFP-NEXT: bl __aeabi_dcmpeq
+; CHECK-MVEFP-NEXT: mov r6, r0
+; CHECK-MVEFP-NEXT: vmov r0, r1, d9
+; CHECK-MVEFP-NEXT: mov r2, r4
+; CHECK-MVEFP-NEXT: mov r3, r5
+; CHECK-MVEFP-NEXT: bl __aeabi_dcmpeq
+; CHECK-MVEFP-NEXT: cmp r0, #0
+; CHECK-MVEFP-NEXT: vldr s1, .LCPI13_1
+; CHECK-MVEFP-NEXT: cset r0, eq
+; CHECK-MVEFP-NEXT: cmp r6, #0
+; CHECK-MVEFP-NEXT: vmov s2, r0
+; CHECK-MVEFP-NEXT: cset r0, eq
+; CHECK-MVEFP-NEXT: vmov s0, r0
+; CHECK-MVEFP-NEXT: vmov.f32 s3, s1
+; CHECK-MVEFP-NEXT: vpop {d8, d9}
+; CHECK-MVEFP-NEXT: pop {r4, r5, r6, pc}
+; CHECK-MVEFP-NEXT: .p2align 3
+; CHECK-MVEFP-NEXT: @ %bb.1:
+; CHECK-MVEFP-NEXT: .LCPI13_0:
+; CHECK-MVEFP-NEXT: .long 0 @ double 0
+; CHECK-MVEFP-NEXT: .long 0
+; CHECK-MVEFP-NEXT: .LCPI13_1:
+; CHECK-MVEFP-NEXT: .long 0x00000000 @ float 0
entry:
%c = fcmp une <2 x double> %src, zeroinitializer
%0 = zext <2 x i1> %c to <2 x i64>
@@ -340,13 +544,31 @@ entry:
define arm_aapcs_vfpcc <4 x float> @uitofp_v4i1_v4f32(<4 x i32> %src) {
-; CHECK-LABEL: uitofp_v4i1_v4f32:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.i32 q1, #0x0
-; CHECK-NEXT: vmov.f32 q2, #1.000000e+00
-; CHECK-NEXT: vcmp.s32 gt, q0, zr
-; CHECK-NEXT: vpsel q0, q2, q1
-; CHECK-NEXT: bx lr
+; CHECK-MVE-LABEL: uitofp_v4i1_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmp.s32 gt, q0, zr
+; CHECK-MVE-NEXT: vmrs r0, p0
+; CHECK-MVE-NEXT: ubfx r2, r0, #12, #1
+; CHECK-MVE-NEXT: ubfx r1, r0, #8, #1
+; CHECK-MVE-NEXT: vmov s0, r2
+; CHECK-MVE-NEXT: ubfx r2, r0, #4, #1
+; CHECK-MVE-NEXT: and r0, r0, #1
+; CHECK-MVE-NEXT: vcvt.f32.u32 s3, s0
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: vcvt.f32.u32 s2, s0
+; CHECK-MVE-NEXT: vmov s0, r2
+; CHECK-MVE-NEXT: vcvt.f32.u32 s1, s0
+; CHECK-MVE-NEXT: vmov s0, r0
+; CHECK-MVE-NEXT: vcvt.f32.u32 s0, s0
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: uitofp_v4i1_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vmov.i32 q1, #0x0
+; CHECK-MVEFP-NEXT: vmov.f32 q2, #1.000000e+00
+; CHECK-MVEFP-NEXT: vcmp.s32 gt, q0, zr
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: bx lr
entry:
%c = icmp sgt <4 x i32> %src, zeroinitializer
%0 = uitofp <4 x i1> %c to <4 x float>
@@ -354,13 +576,35 @@ entry:
}
define arm_aapcs_vfpcc <4 x float> @sitofp_v4i1_v4f32(<4 x i32> %src) {
-; CHECK-LABEL: sitofp_v4i1_v4f32:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.i32 q1, #0x0
-; CHECK-NEXT: vmov.f32 q2, #-1.000000e+00
-; CHECK-NEXT: vcmp.s32 gt, q0, zr
-; CHECK-NEXT: vpsel q0, q2, q1
-; CHECK-NEXT: bx lr
+; CHECK-MVE-LABEL: sitofp_v4i1_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmp.s32 gt, q0, zr
+; CHECK-MVE-NEXT: vmrs r0, p0
+; CHECK-MVE-NEXT: and r1, r0, #1
+; CHECK-MVE-NEXT: ubfx r2, r0, #8, #1
+; CHECK-MVE-NEXT: ubfx r3, r0, #4, #1
+; CHECK-MVE-NEXT: ubfx r0, r0, #12, #1
+; CHECK-MVE-NEXT: rsbs r2, r2, #0
+; CHECK-MVE-NEXT: rsbs r0, r0, #0
+; CHECK-MVE-NEXT: vmov s0, r0
+; CHECK-MVE-NEXT: rsbs r0, r3, #0
+; CHECK-MVE-NEXT: vcvt.f32.s32 s3, s0
+; CHECK-MVE-NEXT: vmov s0, r2
+; CHECK-MVE-NEXT: vcvt.f32.s32 s2, s0
+; CHECK-MVE-NEXT: vmov s0, r0
+; CHECK-MVE-NEXT: rsbs r0, r1, #0
+; CHECK-MVE-NEXT: vcvt.f32.s32 s1, s0
+; CHECK-MVE-NEXT: vmov s0, r0
+; CHECK-MVE-NEXT: vcvt.f32.s32 s0, s0
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: sitofp_v4i1_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vmov.i32 q1, #0x0
+; CHECK-MVEFP-NEXT: vmov.f32 q2, #-1.000000e+00
+; CHECK-MVEFP-NEXT: vcmp.s32 gt, q0, zr
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: bx lr
entry:
%c = icmp sgt <4 x i32> %src, zeroinitializer
%0 = sitofp <4 x i1> %c to <4 x float>
@@ -368,13 +612,39 @@ entry:
}
define arm_aapcs_vfpcc <4 x float> @fptoui_v4i1_v4f32(<4 x float> %src) {
-; CHECK-LABEL: fptoui_v4i1_v4f32:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.i32 q1, #0x0
-; CHECK-NEXT: vmov.f32 q2, #1.000000e+00
-; CHECK-NEXT: vcmp.f32 ne, q0, zr
-; CHECK-NEXT: vpsel q0, q2, q1
-; CHECK-NEXT: bx lr
+; CHECK-MVE-LABEL: fptoui_v4i1_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcvt.s32.f32 s6, s3
+; CHECK-MVE-NEXT: vldr s8, .LCPI20_0
+; CHECK-MVE-NEXT: vcvt.s32.f32 s2, s2
+; CHECK-MVE-NEXT: vcvt.s32.f32 s10, s1
+; CHECK-MVE-NEXT: vmov.f32 s4, #1.000000e+00
+; CHECK-MVE-NEXT: vcvt.s32.f32 s0, s0
+; CHECK-MVE-NEXT: vmov r0, s6
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov r0, s2
+; CHECK-MVE-NEXT: vseleq.f32 s3, s8, s4
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov r0, s10
+; CHECK-MVE-NEXT: vseleq.f32 s2, s8, s4
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vseleq.f32 s1, s8, s4
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
+; CHECK-MVE-NEXT: bx lr
+; CHECK-MVE-NEXT: .p2align 2
+; CHECK-MVE-NEXT: @ %bb.1:
+; CHECK-MVE-NEXT: .LCPI20_0:
+; CHECK-MVE-NEXT: .long 0x00000000 @ float 0
+;
+; CHECK-MVEFP-LABEL: fptoui_v4i1_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vmov.i32 q1, #0x0
+; CHECK-MVEFP-NEXT: vmov.f32 q2, #1.000000e+00
+; CHECK-MVEFP-NEXT: vcmp.f32 ne, q0, zr
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: bx lr
entry:
%0 = fptoui <4 x float> %src to <4 x i1>
%s = select <4 x i1> %0, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float> zeroinitializer
@@ -382,13 +652,39 @@ entry:
}
define arm_aapcs_vfpcc <4 x float> @fptosi_v4i1_v4f32(<4 x float> %src) {
-; CHECK-LABEL: fptosi_v4i1_v4f32:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.i32 q1, #0x0
-; CHECK-NEXT: vmov.f32 q2, #1.000000e+00
-; CHECK-NEXT: vcmp.f32 ne, q0, zr
-; CHECK-NEXT: vpsel q0, q2, q1
-; CHECK-NEXT: bx lr
+; CHECK-MVE-LABEL: fptosi_v4i1_v4f32:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcvt.s32.f32 s8, s3
+; CHECK-MVE-NEXT: vldr s10, .LCPI21_0
+; CHECK-MVE-NEXT: vcvt.s32.f32 s2, s2
+; CHECK-MVE-NEXT: vcvt.s32.f32 s6, s1
+; CHECK-MVE-NEXT: vmov.f32 s4, #1.000000e+00
+; CHECK-MVE-NEXT: vcvt.s32.f32 s0, s0
+; CHECK-MVE-NEXT: vmov r0, s8
+; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: vmov r0, s2
+; CHECK-MVE-NEXT: vseleq.f32 s3, s10, s4
+; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: vmov r0, s6
+; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s4
+; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vseleq.f32 s1, s10, s4
+; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: vseleq.f32 s0, s10, s4
+; CHECK-MVE-NEXT: bx lr
+; CHECK-MVE-NEXT: .p2align 2
+; CHECK-MVE-NEXT: @ %bb.1:
+; CHECK-MVE-NEXT: .LCPI21_0:
+; CHECK-MVE-NEXT: .long 0x00000000 @ float 0
+;
+; CHECK-MVEFP-LABEL: fptosi_v4i1_v4f32:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vmov.i32 q1, #0x0
+; CHECK-MVEFP-NEXT: vmov.f32 q2, #1.000000e+00
+; CHECK-MVEFP-NEXT: vcmp.f32 ne, q0, zr
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: bx lr
entry:
%0 = fptosi <4 x float> %src to <4 x i1>
%s = select <4 x i1> %0, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float> zeroinitializer
@@ -396,13 +692,47 @@ entry:
}
define arm_aapcs_vfpcc <8 x half> @uitofp_v8i1_v8f16(<8 x i16> %src) {
-; CHECK-LABEL: uitofp_v8i1_v8f16:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.i16 q1, #0x0
-; CHECK-NEXT: vmov.i16 q2, #0x3c00
-; CHECK-NEXT: vcmp.s16 gt, q0, zr
-; CHECK-NEXT: vpsel q0, q2, q1
-; CHECK-NEXT: bx lr
+; CHECK-MVE-LABEL: uitofp_v8i1_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmp.s16 gt, q0, zr
+; CHECK-MVE-NEXT: vmrs r0, p0
+; CHECK-MVE-NEXT: and r1, r0, #1
+; CHECK-MVE-NEXT: ubfx r2, r0, #2, #1
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: ubfx r1, r0, #4, #1
+; CHECK-MVE-NEXT: vmov s2, r2
+; CHECK-MVE-NEXT: ubfx r2, r0, #6, #1
+; CHECK-MVE-NEXT: vcvt.f16.u32 s2, s2
+; CHECK-MVE-NEXT: vcvt.f16.u32 s0, s0
+; CHECK-MVE-NEXT: vmov s4, r2
+; CHECK-MVE-NEXT: vins.f16 s0, s2
+; CHECK-MVE-NEXT: vmov s2, r1
+; CHECK-MVE-NEXT: ubfx r1, r0, #8, #1
+; CHECK-MVE-NEXT: ubfx r2, r0, #10, #1
+; CHECK-MVE-NEXT: vcvt.f16.u32 s1, s2
+; CHECK-MVE-NEXT: vcvt.f16.u32 s4, s4
+; CHECK-MVE-NEXT: vmov s2, r1
+; CHECK-MVE-NEXT: ubfx r1, r0, #12, #1
+; CHECK-MVE-NEXT: vins.f16 s1, s4
+; CHECK-MVE-NEXT: vmov s4, r2
+; CHECK-MVE-NEXT: ubfx r0, r0, #14, #1
+; CHECK-MVE-NEXT: vcvt.f16.u32 s4, s4
+; CHECK-MVE-NEXT: vcvt.f16.u32 s2, s2
+; CHECK-MVE-NEXT: vins.f16 s2, s4
+; CHECK-MVE-NEXT: vmov s4, r0
+; CHECK-MVE-NEXT: vmov s6, r1
+; CHECK-MVE-NEXT: vcvt.f16.u32 s4, s4
+; CHECK-MVE-NEXT: vcvt.f16.u32 s3, s6
+; CHECK-MVE-NEXT: vins.f16 s3, s4
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: uitofp_v8i1_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vmov.i16 q1, #0x0
+; CHECK-MVEFP-NEXT: vmov.i16 q2, #0x3c00
+; CHECK-MVEFP-NEXT: vcmp.s16 gt, q0, zr
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: bx lr
entry:
%c = icmp sgt <8 x i16> %src, zeroinitializer
%0 = uitofp <8 x i1> %c to <8 x half>
@@ -410,13 +740,55 @@ entry:
}
define arm_aapcs_vfpcc <8 x half> @sitofp_v8i1_v8f16(<8 x i16> %src) {
-; CHECK-LABEL: sitofp_v8i1_v8f16:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.i16 q1, #0x0
-; CHECK-NEXT: vmov.i16 q2, #0xbc00
-; CHECK-NEXT: vcmp.s16 gt, q0, zr
-; CHECK-NEXT: vpsel q0, q2, q1
-; CHECK-NEXT: bx lr
+; CHECK-MVE-LABEL: sitofp_v8i1_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcmp.s16 gt, q0, zr
+; CHECK-MVE-NEXT: vmrs r0, p0
+; CHECK-MVE-NEXT: and r1, r0, #1
+; CHECK-MVE-NEXT: ubfx r2, r0, #2, #1
+; CHECK-MVE-NEXT: rsbs r1, r1, #0
+; CHECK-MVE-NEXT: rsbs r2, r2, #0
+; CHECK-MVE-NEXT: vmov s0, r2
+; CHECK-MVE-NEXT: ubfx r2, r0, #6, #1
+; CHECK-MVE-NEXT: vcvt.f16.s32 s2, s0
+; CHECK-MVE-NEXT: vmov s0, r1
+; CHECK-MVE-NEXT: ubfx r1, r0, #4, #1
+; CHECK-MVE-NEXT: rsbs r2, r2, #0
+; CHECK-MVE-NEXT: vcvt.f16.s32 s0, s0
+; CHECK-MVE-NEXT: rsbs r1, r1, #0
+; CHECK-MVE-NEXT: vins.f16 s0, s2
+; CHECK-MVE-NEXT: vmov s2, r2
+; CHECK-MVE-NEXT: ubfx r2, r0, #10, #1
+; CHECK-MVE-NEXT: vmov s4, r1
+; CHECK-MVE-NEXT: ubfx r1, r0, #8, #1
+; CHECK-MVE-NEXT: rsbs r2, r2, #0
+; CHECK-MVE-NEXT: vcvt.f16.s32 s2, s2
+; CHECK-MVE-NEXT: vcvt.f16.s32 s1, s4
+; CHECK-MVE-NEXT: rsbs r1, r1, #0
+; CHECK-MVE-NEXT: vins.f16 s1, s2
+; CHECK-MVE-NEXT: vmov s2, r2
+; CHECK-MVE-NEXT: vcvt.f16.s32 s4, s2
+; CHECK-MVE-NEXT: vmov s2, r1
+; CHECK-MVE-NEXT: ubfx r1, r0, #12, #1
+; CHECK-MVE-NEXT: ubfx r0, r0, #14, #1
+; CHECK-MVE-NEXT: rsbs r1, r1, #0
+; CHECK-MVE-NEXT: rsbs r0, r0, #0
+; CHECK-MVE-NEXT: vcvt.f16.s32 s2, s2
+; CHECK-MVE-NEXT: vins.f16 s2, s4
+; CHECK-MVE-NEXT: vmov s4, r0
+; CHECK-MVE-NEXT: vmov s6, r1
+; CHECK-MVE-NEXT: vcvt.f16.s32 s4, s4
+; CHECK-MVE-NEXT: vcvt.f16.s32 s3, s6
+; CHECK-MVE-NEXT: vins.f16 s3, s4
+; CHECK-MVE-NEXT: bx lr
+;
+; CHECK-MVEFP-LABEL: sitofp_v8i1_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vmov.i16 q1, #0x0
+; CHECK-MVEFP-NEXT: vmov.i16 q2, #0xbc00
+; CHECK-MVEFP-NEXT: vcmp.s16 gt, q0, zr
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: bx lr
entry:
%c = icmp sgt <8 x i16> %src, zeroinitializer
%0 = sitofp <8 x i1> %c to <8 x half>
@@ -424,13 +796,63 @@ entry:
}
define arm_aapcs_vfpcc <8 x half> @fptoui_v8i1_v8f16(<8 x half> %src) {
-; CHECK-LABEL: fptoui_v8i1_v8f16:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.i32 q1, #0x0
-; CHECK-NEXT: vmov.i16 q2, #0x3c00
-; CHECK-NEXT: vcmp.f16 ne, q0, zr
-; CHECK-NEXT: vpsel q0, q2, q1
-; CHECK-NEXT: bx lr
+; CHECK-MVE-LABEL: fptoui_v8i1_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcvt.s32.f16 s4, s0
+; CHECK-MVE-NEXT: vmovx.f16 s0, s0
+; CHECK-MVE-NEXT: vcvt.s32.f16 s0, s0
+; CHECK-MVE-NEXT: vldr.16 s8, .LCPI24_0
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vmov.f16 s6, #1.000000e+00
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov r0, s4
+; CHECK-MVE-NEXT: vseleq.f16 s10, s8, s6
+; CHECK-MVE-NEXT: vcvt.s32.f16 s4, s1
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s6
+; CHECK-MVE-NEXT: vins.f16 s0, s10
+; CHECK-MVE-NEXT: vmovx.f16 s10, s1
+; CHECK-MVE-NEXT: vcvt.s32.f16 s10, s10
+; CHECK-MVE-NEXT: vmov r0, s10
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov r0, s4
+; CHECK-MVE-NEXT: vcvt.s32.f16 s4, s2
+; CHECK-MVE-NEXT: vmovx.f16 s2, s2
+; CHECK-MVE-NEXT: vcvt.s32.f16 s2, s2
+; CHECK-MVE-NEXT: vseleq.f16 s10, s8, s6
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov r0, s2
+; CHECK-MVE-NEXT: vseleq.f16 s1, s8, s6
+; CHECK-MVE-NEXT: vins.f16 s1, s10
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov r0, s4
+; CHECK-MVE-NEXT: vseleq.f16 s10, s8, s6
+; CHECK-MVE-NEXT: vcvt.s32.f16 s4, s3
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f16 s2, s8, s6
+; CHECK-MVE-NEXT: vins.f16 s2, s10
+; CHECK-MVE-NEXT: vmovx.f16 s10, s3
+; CHECK-MVE-NEXT: vcvt.s32.f16 s10, s10
+; CHECK-MVE-NEXT: vmov r0, s10
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vmov r0, s4
+; CHECK-MVE-NEXT: vseleq.f16 s10, s8, s6
+; CHECK-MVE-NEXT: cmp r0, #0
+; CHECK-MVE-NEXT: vseleq.f16 s3, s8, s6
+; CHECK-MVE-NEXT: vins.f16 s3, s10
+; CHECK-MVE-NEXT: bx lr
+; CHECK-MVE-NEXT: .p2align 1
+; CHECK-MVE-NEXT: @ %bb.1:
+; CHECK-MVE-NEXT: .LCPI24_0:
+; CHECK-MVE-NEXT: .short 0x0000 @ half 0
+;
+; CHECK-MVEFP-LABEL: fptoui_v8i1_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vmov.i32 q1, #0x0
+; CHECK-MVEFP-NEXT: vmov.i16 q2, #0x3c00
+; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, zr
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: bx lr
entry:
%0 = fptoui <8 x half> %src to <8 x i1>
%s = select <8 x i1> %0, <8 x half> <half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0>, <8 x half> zeroinitializer
@@ -438,13 +860,63 @@ entry:
}
define arm_aapcs_vfpcc <8 x half> @fptosi_v8i1_v8f16(<8 x half> %src) {
-; CHECK-LABEL: fptosi_v8i1_v8f16:
-; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.i32 q1, #0x0
-; CHECK-NEXT: vmov.i16 q2, #0x3c00
-; CHECK-NEXT: vcmp.f16 ne, q0, zr
-; CHECK-NEXT: vpsel q0, q2, q1
-; CHECK-NEXT: bx lr
+; CHECK-MVE-LABEL: fptosi_v8i1_v8f16:
+; CHECK-MVE: @ %bb.0: @ %entry
+; CHECK-MVE-NEXT: vcvt.s32.f16 s4, s0
+; CHECK-MVE-NEXT: vmovx.f16 s0, s0
+; CHECK-MVE-NEXT: vcvt.s32.f16 s0, s0
+; CHECK-MVE-NEXT: vldr.16 s8, .LCPI25_0
+; CHECK-MVE-NEXT: vmov r0, s0
+; CHECK-MVE-NEXT: vmov.f16 s6, #1.000000e+00
+; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: vmov r0, s4
+; CHECK-MVE-NEXT: vseleq.f16 s10, s8, s6
+; CHECK-MVE-NEXT: vcvt.s32.f16 s4, s1
+; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s6
+; CHECK-MVE-NEXT: vins.f16 s0, s10
+; CHECK-MVE-NEXT: vmovx.f16 s10, s1
+; CHECK-MVE-NEXT: vcvt.s32.f16 s10, s10
+; CHECK-MVE-NEXT: vmov r0, s10
+; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: vmov r0, s4
+; CHECK-MVE-NEXT: vcvt.s32.f16 s4, s2
+; CHECK-MVE-NEXT: vmovx.f16 s2, s2
+; CHECK-MVE-NEXT: vseleq.f16 s10, s8, s6
+; CHECK-MVE-NEXT: vcvt.s32.f16 s2, s2
+; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: vmov r0, s2
+; CHECK-MVE-NEXT: vseleq.f16 s1, s8, s6
+; CHECK-MVE-NEXT: vins.f16 s1, s10
+; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: vmov r0, s4
+; CHECK-MVE-NEXT: vseleq.f16 s10, s8, s6
+; CHECK-MVE-NEXT: vcvt.s32.f16 s4, s3
+; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: vseleq.f16 s2, s8, s6
+; CHECK-MVE-NEXT: vins.f16 s2, s10
+; CHECK-MVE-NEXT: vmovx.f16 s10, s3
+; CHECK-MVE-NEXT: vcvt.s32.f16 s10, s10
+; CHECK-MVE-NEXT: vmov r0, s10
+; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: vmov r0, s4
+; CHECK-MVE-NEXT: vseleq.f16 s10, s8, s6
+; CHECK-MVE-NEXT: lsls r0, r0, #31
+; CHECK-MVE-NEXT: vseleq.f16 s3, s8, s6
+; CHECK-MVE-NEXT: vins.f16 s3, s10
+; CHECK-MVE-NEXT: bx lr
+; CHECK-MVE-NEXT: .p2align 1
+; CHECK-MVE-NEXT: @ %bb.1:
+; CHECK-MVE-NEXT: .LCPI25_0:
+; CHECK-MVE-NEXT: .short 0x0000 @ half 0
+;
+; CHECK-MVEFP-LABEL: fptosi_v8i1_v8f16:
+; CHECK-MVEFP: @ %bb.0: @ %entry
+; CHECK-MVEFP-NEXT: vmov.i32 q1, #0x0
+; CHECK-MVEFP-NEXT: vmov.i16 q2, #0x3c00
+; CHECK-MVEFP-NEXT: vcmp.f16 ne, q0, zr
+; CHECK-MVEFP-NEXT: vpsel q0, q2, q1
+; CHECK-MVEFP-NEXT: bx lr
entry:
%0 = fptosi <8 x half> %src to <8 x i1>
%s = select <8 x i1> %0, <8 x half> <half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0, half 1.0>, <8 x half> zeroinitializer
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