[llvm] 46fc4de - [AArch64] Guard FP16 fptosi_sat patterns with HasFullFP16. NFC

[David Green via llvm-commits]

Author: David Green
Date: 2022-07-11T08:35:40+01:00
New Revision: 46fc4de065aada6d41761f5e1b8de72111a8a13c

URL: https://github.com/llvm/llvm-project/commit/46fc4de065aada6d41761f5e1b8de72111a8a13c
DIFF: https://github.com/llvm/llvm-project/commit/46fc4de065aada6d41761f5e1b8de72111a8a13c.diff

LOG: [AArch64] Guard FP16 fptosi_sat patterns with HasFullFP16. NFC

We shouldn't get this far as the operations are already legalized, but
the patterns should be guarded with hasFullFP16.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64InstrInfo.td

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 3802a45ad6c1b..d444223e4494f 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -4356,10 +4356,12 @@ defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", any_fp_to_uint>;
 
 // AArch64's FCVT instructions saturate when out of range.
 multiclass SIMDTwoVectorFPToIntSatPats<SDNode to_int_sat, string INST> {
+  let Predicates = [HasFullFP16] in {
   def : Pat<(v4i16 (to_int_sat v4f16:$Rn, i16)),
             (!cast<Instruction>(INST # v4f16) v4f16:$Rn)>;
   def : Pat<(v8i16 (to_int_sat v8f16:$Rn, i16)),
             (!cast<Instruction>(INST # v8f16) v8f16:$Rn)>;
+  }
   def : Pat<(v2i32 (to_int_sat v2f32:$Rn, i32)),
             (!cast<Instruction>(INST # v2f32) v2f32:$Rn)>;
   def : Pat<(v4i32 (to_int_sat v4f32:$Rn, i32)),