[PATCH] D129463: [RISCV][test] Precommit test for D129179.
Jianjian Guan via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Jul 10 23:47:25 PDT 2022
jacquesguan created this revision.
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Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D129463
Files:
llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
Index: llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
+++ llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
@@ -373,3 +373,57 @@
%v8 = alloca <vscale x 8 x i1>
ret void
}
+
+define void @lmul_8_x5() nounwind {
+; CHECK-LABEL: lmul_8_x5:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -80
+; CHECK-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
+; CHECK-NEXT: addi s0, sp, 80
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a1, 40
+; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: sub sp, sp, a0
+; CHECK-NEXT: andi sp, sp, -64
+; CHECK-NEXT: addi sp, s0, -80
+; CHECK-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
+; CHECK-NEXT: addi sp, sp, 80
+; CHECK-NEXT: ret
+ %v1 = alloca <vscale x 8 x i64>
+ %v2 = alloca <vscale x 8 x i64>
+ %v3 = alloca <vscale x 8 x i64>
+ %v4 = alloca <vscale x 8 x i64>
+ %v5 = alloca <vscale x 8 x i64>
+ ret void
+}
+
+define void @lmul_8_x9() nounwind {
+; CHECK-LABEL: lmul_8_x9:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -80
+; CHECK-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
+; CHECK-NEXT: sd s0, 64(sp) # 8-byte Folded Spill
+; CHECK-NEXT: addi s0, sp, 80
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a1, 72
+; CHECK-NEXT: mul a0, a0, a1
+; CHECK-NEXT: sub sp, sp, a0
+; CHECK-NEXT: andi sp, sp, -64
+; CHECK-NEXT: addi sp, s0, -80
+; CHECK-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
+; CHECK-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
+; CHECK-NEXT: addi sp, sp, 80
+; CHECK-NEXT: ret
+ %v1 = alloca <vscale x 8 x i64>
+ %v2 = alloca <vscale x 8 x i64>
+ %v3 = alloca <vscale x 8 x i64>
+ %v4 = alloca <vscale x 8 x i64>
+ %v5 = alloca <vscale x 8 x i64>
+ %v6 = alloca <vscale x 8 x i64>
+ %v7 = alloca <vscale x 8 x i64>
+ %v8 = alloca <vscale x 8 x i64>
+ %v9 = alloca <vscale x 8 x i64>
+ ret void
+}
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