[PATCH] D129449: [AArch64] Update latencies for Cortex-A55 schedule.

Dave Green via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sun Jul 10 10:03:15 PDT 2022 

dmgreen created this revision.
dmgreen added reviewers: SjoerdMeijer, samtebbs, kristof.beyls, t.p.northover, NickGuy.
Herald added subscribers: armkevincheng, eric-k256, asbirlea, arphaman, gbedwell, hiraditya, arichardson.
Herald added a reviewer: andreadb.
Herald added a reviewer: sjarus.
Herald added a project: All.
dmgreen requested review of this revision.
Herald added a project: LLVM.

The Cortex-A55 schedule currently attempts to model a lot of the effective latencies by marking most integer instructions as having a latency of 3, and then adding forwarding latencies between classes of instructions. When this works it does OK, but is very easy to either get the effective latencies wrong or be tripped up by instructions like pseudo instructions that knock the latency back to 3 without considering forwarding.  That in turn can make the decisions it makes suboptimal. This patch simplifies that by just setting the latencies more directly, lining the latencies up with the values from the Software Optimization Guide. In reality the core is more sophisticated than either scheme.

As expected for the AArch64 default schedule, this alters quite a lot of codegen. Almost all of the tests are the same instructions in a slightly different order. The ones with interesting differences are:

- andorbrcompare.ll - Now choses ccmp vs branch, due to some bad use of latencies in the AArch64ConditionalCompares pass.
- arm64-ldp.ll - Now uses more postinc. Yay.
- arm64-neon-mul-div.ll - Has slightly more spills. Boo.
- Some other changes like this, where there are slightly less or more instructions.
- neon-mla-mls.ll - Chooses mul;sub as opposed to neg;mla. I believe this is generally better, and the differences are coming from better considering of COPYs.
- llvm-mca tests no longer show instructions taking three cycles.

For all the measurements I've been collecting, the performance is on average between flat and a slight performance increase, depending on the core and the benchmarks being run. The knock-on effects from different instruction ordering can make any individual test better or worse, but from a range of benchmarks they tend to roughly average one another out.


https://reviews.llvm.org/D129449

Files:
  llvm/lib/Target/AArch64/AArch64SchedA55.td
  llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
  llvm/test/CodeGen/AArch64/GlobalISel/call-translator-variadic-musttail.ll
  llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
  llvm/test/CodeGen/AArch64/GlobalISel/select-bitfield-insert.ll
  llvm/test/CodeGen/AArch64/GlobalISel/store-merging.ll
  llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll
  llvm/test/CodeGen/AArch64/aarch64-be-bv.ll
  llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
  llvm/test/CodeGen/AArch64/aarch64-load-ext.ll
  llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
  llvm/test/CodeGen/AArch64/aarch64-mops-consecutive.ll
  llvm/test/CodeGen/AArch64/aarch64-smull.ll
  llvm/test/CodeGen/AArch64/aarch64-tail-dup-size.ll
  llvm/test/CodeGen/AArch64/aarch64_win64cc_vararg.ll
  llvm/test/CodeGen/AArch64/active_lane_mask.ll
  llvm/test/CodeGen/AArch64/align-down.ll
  llvm/test/CodeGen/AArch64/and-mask-removal.ll
  llvm/test/CodeGen/AArch64/andorbrcompare.ll
  llvm/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll
  llvm/test/CodeGen/AArch64/arm64-addr-type-promotion.ll
  llvm/test/CodeGen/AArch64/arm64-addrmode.ll
  llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll
  llvm/test/CodeGen/AArch64/arm64-cse.ll
  llvm/test/CodeGen/AArch64/arm64-fcopysign.ll
  llvm/test/CodeGen/AArch64/arm64-fmadd.ll
  llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-no-helper.ll
  llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
  llvm/test/CodeGen/AArch64/arm64-inline-asm.ll
  llvm/test/CodeGen/AArch64/arm64-instruction-mix-remarks.ll
  llvm/test/CodeGen/AArch64/arm64-ldp.ll
  llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
  llvm/test/CodeGen/AArch64/arm64-neon-mul-div.ll
  llvm/test/CodeGen/AArch64/arm64-neon-vector-shuffle-extract.ll
  llvm/test/CodeGen/AArch64/arm64-nvcast.ll
  llvm/test/CodeGen/AArch64/arm64-rev.ll
  llvm/test/CodeGen/AArch64/arm64-setcc-int-to-fp-combine.ll
  llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll
  llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
  llvm/test/CodeGen/AArch64/arm64-tls-dynamics.ll
  llvm/test/CodeGen/AArch64/arm64-vabs.ll
  llvm/test/CodeGen/AArch64/arm64-vhadd.ll
  llvm/test/CodeGen/AArch64/arm64-vmul.ll
  llvm/test/CodeGen/AArch64/arm64-xaluo.ll
  llvm/test/CodeGen/AArch64/arm64_32-addrs.ll
  llvm/test/CodeGen/AArch64/arm64_32.ll
  llvm/test/CodeGen/AArch64/atomic-ops-lse.ll
  llvm/test/CodeGen/AArch64/bfis-in-loop.ll
  llvm/test/CodeGen/AArch64/bitfield-insert.ll
  llvm/test/CodeGen/AArch64/branch-relax-bcc.ll
  llvm/test/CodeGen/AArch64/build-one-lane.ll
  llvm/test/CodeGen/AArch64/build-vector-extract.ll
  llvm/test/CodeGen/AArch64/cgp-usubo.ll
  llvm/test/CodeGen/AArch64/cmp-select-sign.ll
  llvm/test/CodeGen/AArch64/combine-mul.ll
  llvm/test/CodeGen/AArch64/consthoist-gep.ll
  llvm/test/CodeGen/AArch64/copyprop.ll
  llvm/test/CodeGen/AArch64/ctpop-nonean.ll
  llvm/test/CodeGen/AArch64/dag-numsignbits.ll
  llvm/test/CodeGen/AArch64/div-rem-pair-recomposition-signed.ll
  llvm/test/CodeGen/AArch64/div-rem-pair-recomposition-unsigned.ll
  llvm/test/CodeGen/AArch64/expand-select.ll
  llvm/test/CodeGen/AArch64/extract-bits.ll
  llvm/test/CodeGen/AArch64/extract-lowbits.ll
  llvm/test/CodeGen/AArch64/faddp.ll
  llvm/test/CodeGen/AArch64/fast-isel-addressing-modes.ll
  llvm/test/CodeGen/AArch64/fast-isel-gep.ll
  llvm/test/CodeGen/AArch64/fast-isel-memcpy.ll
  llvm/test/CodeGen/AArch64/fast-isel-shift.ll
  llvm/test/CodeGen/AArch64/fcvt_combine.ll
  llvm/test/CodeGen/AArch64/fold-csel-cttz-and.ll
  llvm/test/CodeGen/AArch64/fold-global-offsets.ll
  llvm/test/CodeGen/AArch64/fp-intrinsics-vector.ll
  llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
  llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
  llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
  llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
  llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll
  llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
  llvm/test/CodeGen/AArch64/funnel-shift-rot.ll
  llvm/test/CodeGen/AArch64/funnel-shift.ll
  llvm/test/CodeGen/AArch64/global-merge-3.ll
  llvm/test/CodeGen/AArch64/global-merge-group-by-use.ll
  llvm/test/CodeGen/AArch64/global-merge-ignore-single-use-minsize.ll
  llvm/test/CodeGen/AArch64/half.ll
  llvm/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
  llvm/test/CodeGen/AArch64/i128-math.ll
  llvm/test/CodeGen/AArch64/i128_volatile_load_store.ll
  llvm/test/CodeGen/AArch64/i256-math.ll
  llvm/test/CodeGen/AArch64/icmp-shift-opt.ll
  llvm/test/CodeGen/AArch64/insert-extend.ll
  llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
  llvm/test/CodeGen/AArch64/insert-subvector.ll
  llvm/test/CodeGen/AArch64/isinf.ll
  llvm/test/CodeGen/AArch64/known-never-nan.ll
  llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll
  llvm/test/CodeGen/AArch64/logic-reassociate.ll
  llvm/test/CodeGen/AArch64/logic-shift.ll
  llvm/test/CodeGen/AArch64/logical_shifted_reg.ll
  llvm/test/CodeGen/AArch64/lowerMUL-newload.ll
  llvm/test/CodeGen/AArch64/machine-combiner-copy.ll
  llvm/test/CodeGen/AArch64/machine-combiner-subadd.ll
  llvm/test/CodeGen/AArch64/machine-licm-sink-instr.ll
  llvm/test/CodeGen/AArch64/memcpy-scoped-aa.ll
  llvm/test/CodeGen/AArch64/merge-trunc-store.ll
  llvm/test/CodeGen/AArch64/midpoint-int.ll
  llvm/test/CodeGen/AArch64/minmax-of-minmax.ll
  llvm/test/CodeGen/AArch64/minmax.ll
  llvm/test/CodeGen/AArch64/misched-fusion-lit.ll
  llvm/test/CodeGen/AArch64/mul_pow2.ll
  llvm/test/CodeGen/AArch64/named-vector-shuffles-neon.ll
  llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
  llvm/test/CodeGen/AArch64/neg-imm.ll
  llvm/test/CodeGen/AArch64/neon-abd.ll
  llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
  llvm/test/CodeGen/AArch64/neon-dotreduce.ll
  llvm/test/CodeGen/AArch64/neon-extadd.ll
  llvm/test/CodeGen/AArch64/neon-extracttruncate.ll
  llvm/test/CodeGen/AArch64/neon-mla-mls.ll
  llvm/test/CodeGen/AArch64/neon-reverseshuffle.ll
  llvm/test/CodeGen/AArch64/neon-stepvector.ll
  llvm/test/CodeGen/AArch64/neon-truncstore.ll
  llvm/test/CodeGen/AArch64/neon-wide-splat.ll
  llvm/test/CodeGen/AArch64/neon-widen-shuffle.ll
  llvm/test/CodeGen/AArch64/nontemporal.ll
  llvm/test/CodeGen/AArch64/nzcv-save.ll
  llvm/test/CodeGen/AArch64/overeager_mla_fusing.ll
  llvm/test/CodeGen/AArch64/peephole-and-tst.ll
  llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
  llvm/test/CodeGen/AArch64/rand.ll
  llvm/test/CodeGen/AArch64/reduce-and.ll
  llvm/test/CodeGen/AArch64/reduce-or.ll
  llvm/test/CodeGen/AArch64/reduce-shuffle.ll
  llvm/test/CodeGen/AArch64/reduce-xor.ll
  llvm/test/CodeGen/AArch64/regress-tblgen-chains.ll
  llvm/test/CodeGen/AArch64/rotate-extract.ll
  llvm/test/CodeGen/AArch64/sadd_sat_plus.ll
  llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
  llvm/test/CodeGen/AArch64/sat-add.ll
  llvm/test/CodeGen/AArch64/select-constant-xor.ll
  llvm/test/CodeGen/AArch64/select-with-and-or.ll
  llvm/test/CodeGen/AArch64/select_const.ll
  llvm/test/CodeGen/AArch64/select_fmf.ll
  llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll
  llvm/test/CodeGen/AArch64/settag-merge-order.ll
  llvm/test/CodeGen/AArch64/settag-merge.ll
  llvm/test/CodeGen/AArch64/settag.ll
  llvm/test/CodeGen/AArch64/shift-amount-mod.ll
  llvm/test/CodeGen/AArch64/shift-by-signext.ll
  llvm/test/CodeGen/AArch64/shift_minsize.ll
  llvm/test/CodeGen/AArch64/shuffle-tbl34.ll
  llvm/test/CodeGen/AArch64/shuffles.ll
  llvm/test/CodeGen/AArch64/sink-addsub-of-const.ll
  llvm/test/CodeGen/AArch64/sinksplat.ll
  llvm/test/CodeGen/AArch64/sitofp-fixed-legal.ll
  llvm/test/CodeGen/AArch64/sme-intrinsics-loads.ll
  llvm/test/CodeGen/AArch64/sme-intrinsics-mova-extract.ll
  llvm/test/CodeGen/AArch64/sme-intrinsics-mova-insert.ll
  llvm/test/CodeGen/AArch64/sme-intrinsics-stores.ll
  llvm/test/CodeGen/AArch64/speculation-hardening-loads.ll
  llvm/test/CodeGen/AArch64/split-vector-insert.ll
  llvm/test/CodeGen/AArch64/sqrt-fastmath.ll
  llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll
  llvm/test/CodeGen/AArch64/srem-seteq-vec-nonsplat.ll
  llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll
  llvm/test/CodeGen/AArch64/srem-vector-lkk.ll
  llvm/test/CodeGen/AArch64/sshl_sat.ll
  llvm/test/CodeGen/AArch64/ssub_sat_plus.ll
  llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
  llvm/test/CodeGen/AArch64/stack-guard-sysreg.ll
  llvm/test/CodeGen/AArch64/statepoint-call-lowering.ll
  llvm/test/CodeGen/AArch64/sve-abd.ll
  llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll
  llvm/test/CodeGen/AArch64/sve-extract-element.ll
  llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
  llvm/test/CodeGen/AArch64/sve-extract-scalable-vector.ll
  llvm/test/CodeGen/AArch64/sve-fcopysign.ll
  llvm/test/CodeGen/AArch64/sve-fix-length-and-combine-512.ll
  llvm/test/CodeGen/AArch64/sve-fixed-ld2-alloca.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-bit-counting.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-extract-subvector.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-select.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-frame-offests-crash.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-insert-vector-elt.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-arith.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-compares.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-log.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-minmax.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-mulh.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-reduce.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-select.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-shifts.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-vselect.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-loads.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-log-reduce.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-loads.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-scatter.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-masked-stores.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-permute-rev.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-rev.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-sdiv-pow2.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-shuffles.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-splat-vector.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-stores.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle.ll
  llvm/test/CodeGen/AArch64/sve-fp-reduce.ll
  llvm/test/CodeGen/AArch64/sve-gather-scatter-addr-opts.ll
  llvm/test/CodeGen/AArch64/sve-implicit-zero-filling.ll
  llvm/test/CodeGen/AArch64/sve-insert-element.ll
  llvm/test/CodeGen/AArch64/sve-insert-vector.ll
  llvm/test/CodeGen/AArch64/sve-int-arith.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems-i32.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-index.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
  llvm/test/CodeGen/AArch64/sve-ld-post-inc.ll
  llvm/test/CodeGen/AArch64/sve-ld1r.ll
  llvm/test/CodeGen/AArch64/sve-masked-ldst-sext.ll
  llvm/test/CodeGen/AArch64/sve-select.ll
  llvm/test/CodeGen/AArch64/sve-split-extract-elt.ll
  llvm/test/CodeGen/AArch64/sve-split-fcvt.ll
  llvm/test/CodeGen/AArch64/sve-split-fp-reduce.ll
  llvm/test/CodeGen/AArch64/sve-split-insert-elt.ll
  llvm/test/CodeGen/AArch64/sve-split-int-pred-reduce.ll
  llvm/test/CodeGen/AArch64/sve-split-int-reduce.ll
  llvm/test/CodeGen/AArch64/sve-split-load.ll
  llvm/test/CodeGen/AArch64/sve-srem-combine-loop.ll
  llvm/test/CodeGen/AArch64/sve-stepvector.ll
  llvm/test/CodeGen/AArch64/sve-trunc.ll
  llvm/test/CodeGen/AArch64/sve-umulo-sdnode.ll
  llvm/test/CodeGen/AArch64/sve-vecreduce-fold.ll
  llvm/test/CodeGen/AArch64/sve-vector-splat.ll
  llvm/test/CodeGen/AArch64/sve2-fcopysign.ll
  llvm/test/CodeGen/AArch64/swifterror.ll
  llvm/test/CodeGen/AArch64/tbl-loops.ll
  llvm/test/CodeGen/AArch64/typepromotion-overflow.ll
  llvm/test/CodeGen/AArch64/typepromotion-phisret.ll
  llvm/test/CodeGen/AArch64/typepromotion-signed.ll
  llvm/test/CodeGen/AArch64/uadd_sat_plus.ll
  llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
  llvm/test/CodeGen/AArch64/udivmodei5.ll
  llvm/test/CodeGen/AArch64/umulo-128-legalisation-lowering.ll
  llvm/test/CodeGen/AArch64/urem-lkk.ll
  llvm/test/CodeGen/AArch64/urem-seteq-illegal-types.ll
  (45 more files...)

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