[llvm] 5f7641a - [RISCV] Modify the custom isel for (add X, imm) used by load/stores.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-07-09T22:47:27-07:00
New Revision: 5f7641a3be2ed916a6e25a2ad92cfd2b1cd603d1

URL: https://github.com/llvm/llvm-project/commit/5f7641a3be2ed916a6e25a2ad92cfd2b1cd603d1
DIFF: https://github.com/llvm/llvm-project/commit/5f7641a3be2ed916a6e25a2ad92cfd2b1cd603d1.diff

LOG: [RISCV] Modify the custom isel for (add X, imm) used by load/stores.

We have custom isel that tries to select the Lo12 bits using a
separate ADDI that can later folded into the load/store address
by the post-isel peephole.

This patch disables this if the load/store already had a non-zero
offset. A non-zero offset implies that CodeGenPrepare split several
large offsets used by different loads and stores into a common large
offset and multiple small offsets that could be folded. Folding more
of the lo12 bits changes this common offset by increasing the small
offsets. While this can save an instruction to materialize the common
offset, it can also prevent the small offsets from fitting in a
compressed load/store instruction.

Removing this also simplifies the last piece needed to fold the custom
isel for add into SelectAddrRegImm and remove the post-isel peephole.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    llvm/test/CodeGen/RISCV/split-offsets.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 42ee859a0d957..14c1da2ceb495 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -705,12 +705,10 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
         break;
       }
 
-      // If the memory instruction already has an offset, make sure the combined
-      // offset is foldable.
+      // If the memory instruction already has an offset, don't allow folding.
       int64_t MemOffs =
           cast<ConstantSDNode>(User->getOperand(OffsetOpIdx))->getSExtValue();
-      MemOffs += Lo12;
-      if (!isInt<12>(MemOffs)) {
+      if (MemOffs != 0) {
         AllPointerUses = false;
         break;
       }

diff  --git a/llvm/test/CodeGen/RISCV/split-offsets.ll b/llvm/test/CodeGen/RISCV/split-offsets.ll
index 2510baf386e2d..1d5e9aa1f4327 100644
--- a/llvm/test/CodeGen/RISCV/split-offsets.ll
+++ b/llvm/test/CodeGen/RISCV/split-offsets.ll
@@ -13,28 +13,30 @@ define void @test1([65536 x i32]** %sp, [65536 x i32]* %t, i32 %n) {
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lw a0, 0(a0)
 ; RV32I-NEXT:    lui a2, 20
+; RV32I-NEXT:    addi a2, a2, -1920
 ; RV32I-NEXT:    add a1, a1, a2
 ; RV32I-NEXT:    add a0, a0, a2
 ; RV32I-NEXT:    li a2, 2
-; RV32I-NEXT:    sw a2, -1920(a0)
+; RV32I-NEXT:    sw a2, 0(a0)
 ; RV32I-NEXT:    li a3, 1
-; RV32I-NEXT:    sw a3, -1916(a0)
-; RV32I-NEXT:    sw a3, -1920(a1)
-; RV32I-NEXT:    sw a2, -1916(a1)
+; RV32I-NEXT:    sw a3, 4(a0)
+; RV32I-NEXT:    sw a3, 0(a1)
+; RV32I-NEXT:    sw a2, 4(a1)
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: test1:
 ; RV64I:       # %bb.0: # %entry
 ; RV64I-NEXT:    ld a0, 0(a0)
 ; RV64I-NEXT:    lui a2, 20
+; RV64I-NEXT:    addiw a2, a2, -1920
 ; RV64I-NEXT:    add a1, a1, a2
 ; RV64I-NEXT:    add a0, a0, a2
 ; RV64I-NEXT:    li a2, 2
-; RV64I-NEXT:    sw a2, -1920(a0)
+; RV64I-NEXT:    sw a2, 0(a0)
 ; RV64I-NEXT:    li a3, 1
-; RV64I-NEXT:    sw a3, -1916(a0)
-; RV64I-NEXT:    sw a3, -1920(a1)
-; RV64I-NEXT:    sw a2, -1916(a1)
+; RV64I-NEXT:    sw a3, 4(a0)
+; RV64I-NEXT:    sw a3, 0(a1)
+; RV64I-NEXT:    sw a2, 4(a1)
 ; RV64I-NEXT:    ret
 entry:
   %s = load [65536 x i32]*, [65536 x i32]** %sp
@@ -123,21 +125,23 @@ define void @test3([65536 x i32]* %t) {
 ; RV32I-LABEL: test3:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    lui a1, 20
+; RV32I-NEXT:    addi a1, a1, -1920
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    li a1, 2
-; RV32I-NEXT:    sw a1, -1916(a0)
+; RV32I-NEXT:    sw a1, 4(a0)
 ; RV32I-NEXT:    li a1, 3
-; RV32I-NEXT:    sw a1, -1912(a0)
+; RV32I-NEXT:    sw a1, 8(a0)
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: test3:
 ; RV64I:       # %bb.0: # %entry
 ; RV64I-NEXT:    lui a1, 20
+; RV64I-NEXT:    addiw a1, a1, -1920
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    li a1, 2
-; RV64I-NEXT:    sw a1, -1916(a0)
+; RV64I-NEXT:    sw a1, 4(a0)
 ; RV64I-NEXT:    li a1, 3
-; RV64I-NEXT:    sw a1, -1912(a0)
+; RV64I-NEXT:    sw a1, 8(a0)
 ; RV64I-NEXT:    ret
 entry:
   %0 = bitcast [65536 x i32]* %t to i8*