[llvm] eba6d92 - Replace hard coded number with regex so the test passes on downstream projects that may define additional opcodes.

[Douglas Yung via llvm-commits]

Author: Douglas Yung
Date: 2022-07-08T15:49:37-07:00
New Revision: eba6d92f697c5c36fcbd3417c010c69a5348f0a8

URL: https://github.com/llvm/llvm-project/commit/eba6d92f697c5c36fcbd3417c010c69a5348f0a8
DIFF: https://github.com/llvm/llvm-project/commit/eba6d92f697c5c36fcbd3417c010c69a5348f0a8.diff

LOG: Replace hard coded number with regex so the test passes on downstream projects that may define additional opcodes.

Added: 
    

Modified: 
    llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir

Removed: 
    


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diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index db5a4c0a684c5..725baf0f620f4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -161,7 +161,7 @@
 # DEBUG-NEXT: G_SEXTLOAD (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
-# DEBUG-NEXT: G_ZEXTLOAD (opcode 80): 2 type indices, 0 imm indices
+# DEBUG-NEXT: G_ZEXTLOAD (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: G_INDEXED_LOAD (opcode {{[0-9]+}}): 3 type indices, 0 imm indices