[PATCH] D129381: [AMDGPU][CodeGen] Support (register + immediate) SMRD offsets.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/amdgcn-load-offset-from-reg.ll:1-2
-; RUN: llc -march=amdgcn -global-isel=0 -verify-machineinstrs -stop-after=amdgpu-isel -o - %s | FileCheck -check-prefixes=GCN,SDAG %s
-; RUN: llc -march=amdgcn -global-isel=1 -verify-machineinstrs -stop-after=amdgpu-isel -o - %s | FileCheck -check-prefixes=GCN,GISEL %s
+; RUN: llc -march=amdgcn -mcpu=gfx900 -global-isel=0 -verify-machineinstrs -stop-after=amdgpu-isel -o - %s | FileCheck -check-prefixes=GCN,SDAG %s
+; RUN: llc -march=amdgcn -mcpu=gfx900 -global-isel=1 -verify-machineinstrs -stop-after=amdgpu-isel -o - %s | FileCheck -check-prefixes=GCN,GISEL %s
 
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You shouldn't use -stop-after=amdgpu-isel. Use finalize-isel for MIR tests (although I'm not sure why you're testing MIR here)


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Comment at: llvm/test/CodeGen/AMDGPU/amdgcn-load-offset-from-reg.ll:65
+  %v4 = bitcast i8 addrspace(4)* %v3 to i32 addrspace(4)*
+  %v5 = load i32, i32 addrspace(4)* %v4, align 4
+  store i32 %v5, i32 addrspace(1)* %out, align 4
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Also test some other load sizes?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129381/new/

https://reviews.llvm.org/D129381