[PATCH] D129372: [DebugInfo][NFC?] Add new MachineOperand type and change DBG_INSTR_REF syntax

Fri Jul 8 07:19:08 PDT 2022

StephenTozer created this revision.
StephenTozer added reviewers: jmorse, Orlando.
StephenTozer added a project: debug-info.
Herald added subscribers: jsji, jdoerfert, pengfei, hiraditya, qcolombet, MatzeB.
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StephenTozer requested review of this revision.
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This patch implements the proposals in the RFC made earlier this year <https://discourse.llvm.org/t/rfc-adding-a-new-machine-operand-type-to-implement-variadic-dbg-instr-ref-instructions/61349>.

This patch makes two notable changes to the MIR debug info representation, which result in different MIR output but identical final DWARF output (NFC w.r.t. the full compilation). The two changes are:

1. The introduction of a new MachineOperand type, `MO_DbgInstrRef`, which consists of two unsigned numbers that are used to index an instruction and an output operand within that instruction, having a meaning identical to first two operands of the current `DBG_INSTR_REF` instruction. This operand is only used in `DBG_INSTR_REF` (see below).
2. A change in syntax for the `DBG_INSTR_REF` instruction, shuffling the operands to make it resemble `DBG_VALUE_LIST` instead of `DBG_VALUE`, and replacing the first two operands with a single `MO_DbgInstrRef`-type operand.

Combined, these changes do not affect anything about the debug info that we produce or how we handle it throughout CodeGen, but instead simply changes the way we represent instruction references:

  Old: DBG_INSTR_REF 1, 0, !123, !456
  New: DBG_INSTR_REF !123, !456, dbg-instr-ref(1, 0)

The motivation for this, as described in the RFC, is that we wish to be able to use instruction references in variadic debug values. One of the key difficulties with variadic debug values is that they must track the lifetimes of every register that they refer to, making them brittle to things like hoisting or sinking instructions - even if there is a valid range where a variadic debug value can be computed, the debug value may be terminated by shuffling instructions. As instruction references are more resilient against this sort of thing by referring to values produced by instructions instead of registers, freeing us from the need to move the debug values themselves around and preemptively terminate their ranges, it may be beneficial to allow variadic debug values to take advantage of this behaviour.

This patch does not grant this functionality, but takes care of all the foundational work to implement this feature, allowing the next patch to focus entirely on functional changes.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D129372

Files:
  llvm/docs/MIRLangRef.rst
  llvm/include/llvm/CodeGen/MachineInstr.h
  llvm/include/llvm/CodeGen/MachineOperand.h
  llvm/lib/CodeGen/InlineSpiller.cpp
  llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
  llvm/lib/CodeGen/LiveDebugVariables.cpp
  llvm/lib/CodeGen/MIRParser/MILexer.cpp
  llvm/lib/CodeGen/MIRParser/MILexer.h
  llvm/lib/CodeGen/MIRParser/MIParser.cpp
  llvm/lib/CodeGen/MIRPrinter.cpp
  llvm/lib/CodeGen/MachineFunction.cpp
  llvm/lib/CodeGen/MachineInstr.cpp
  llvm/lib/CodeGen/MachineOperand.cpp
  llvm/lib/CodeGen/MachineSink.cpp
  llvm/lib/CodeGen/MachineStableHash.cpp
  llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
  llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
  llvm/test/CodeGen/X86/dbg-value-superreg-copy2.mir
  llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir
  llvm/test/DebugInfo/AArch64/instr-ref-const-physreg.ll
  llvm/test/DebugInfo/ARM/instr-ref-tcreturn.ll
  llvm/test/DebugInfo/MIR/InstrRef/accept-nonlive-reg-phis.mir
  llvm/test/DebugInfo/MIR/InstrRef/dbg-phi-subregister-location.mir
  llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv.mir
  llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv2.mir
  llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-merging-in-ldv.mir
  llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-with-loops.mir
  llvm/test/DebugInfo/MIR/InstrRef/deref-spills-with-size.mir
  llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-live-value.mir
  llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir
  llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir
  llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_stackslot_subregs.mir
  llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_subreg_substitutions.mir
  llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir
  llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding.mir
  llvm/test/DebugInfo/MIR/InstrRef/memory-operand-load-folding.mir
  llvm/test/DebugInfo/MIR/InstrRef/memory-operand-tracking.mir
  llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir
  llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir
  llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir
  llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced.mir
  llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced2.mir
  llvm/test/DebugInfo/MIR/InstrRef/phi-regallocd-to-stack.mir
  llvm/test/DebugInfo/MIR/InstrRef/phi-through-regalloc.mir
  llvm/test/DebugInfo/MIR/InstrRef/pick-vphi-in-shifting-loop.mir
  llvm/test/DebugInfo/MIR/InstrRef/spill-slot-limits.mir
  llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir
  llvm/test/DebugInfo/MIR/InstrRef/substitusions-roundtrip.mir
  llvm/test/DebugInfo/MIR/InstrRef/survives-livedebugvars.mir
  llvm/test/DebugInfo/MIR/InstrRef/twoaddr-to-threeaddr-sub.mir
  llvm/test/DebugInfo/MIR/InstrRef/win32-chkctk-modifies-esp.mir
  llvm/test/DebugInfo/MIR/InstrRef/x86-drop-compare-inst.mir
  llvm/test/DebugInfo/X86/dbg-value-arg-movement.ll
  llvm/test/DebugInfo/X86/dbg-value-funcarg.ll
  llvm/test/DebugInfo/X86/dbg-value-funcarg2.ll
  llvm/test/DebugInfo/X86/dbg-value-funcarg4.ll
  llvm/test/DebugInfo/X86/instr-ref-dbg-declare.ll
  llvm/test/DebugInfo/X86/instr-ref-dyn-alloca-win32.ll
  llvm/test/DebugInfo/X86/instr-ref-ir-reg-read.ll
  llvm/test/DebugInfo/X86/instr-ref-sdag-empty-vreg.ll
  llvm/test/DebugInfo/X86/instr-ref-selectiondag.ll
  llvm/test/DebugInfo/X86/pr34545.ll
  llvm/test/DebugInfo/X86/pr40427.ll
  llvm/test/DebugInfo/X86/sdag-dangling-dbgvalue.ll
  llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-1.ll
  llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-2.ll
  llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-3.ll
  llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-4.ll
  llvm/test/DebugInfo/X86/sdag-dbgvalue-ssareg.ll
  llvm/test/DebugInfo/X86/sdag-ir-salvage.ll
  llvm/test/DebugInfo/X86/sdag-salvage-add.ll
  llvm/test/DebugInfo/X86/sdag-transfer-dbgvalue.ll

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