[llvm] 7b9a3b9 - [RISCV] Precommit testcase to show wrong result of make-compressible optimization

[Kito Cheng via llvm-commits]

Author: Kito Cheng
Date: 2022-07-08T17:01:22+08:00
New Revision: 7b9a3b9d6d98184d3e20c03fceefaac6dc0c3580

URL: https://github.com/llvm/llvm-project/commit/7b9a3b9d6d98184d3e20c03fceefaac6dc0c3580
DIFF: https://github.com/llvm/llvm-project/commit/7b9a3b9d6d98184d3e20c03fceefaac6dc0c3580.diff

LOG: [RISCV] Precommit testcase to show wrong result of make-compressible optimization

Use following example to demo what happened now:

  li      a1, 1
  sd      a1, 800(a0)
  sd      a0, 808(a0) # Store base address into base + offset
  li      a1, 2
  sd      a1, 816(a0)

Current will optimizate into:

  li      a1, 1
  addi    a2, a0, 768
  sd      a1, 32(a2)
  sd      a2, 40(a2) # Wrong replacement for the source register.
  li      a1, 2
  sd      a1, 48(a2)

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D128875

Added: 
    llvm/test/CodeGen/RISCV/make-compressible-for-store-address.mir

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/make-compressible-for-store-address.mir b/llvm/test/CodeGen/RISCV/make-compressible-for-store-address.mir
new file mode 100644
index 000000000000..a913fcb6f609
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/make-compressible-for-store-address.mir
@@ -0,0 +1,47 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -o - %s -mtriple=riscv64 -mattr=+c -simplify-mir \
+# RUN:   -run-pass=riscv-make-compressible | FileCheck %s
+--- |
+  define void @foo(ptr noundef %ptr) #0 {
+  entry:
+    %0 = ptrtoint ptr %ptr to i64
+    %1 = getelementptr inbounds i64, ptr %ptr, i64 100
+    store i64 1, ptr %1, align 8
+    %2 = getelementptr inbounds i64, ptr %ptr, i64 101
+    store i64 %0, ptr %2, align 8
+    %3 = getelementptr inbounds i64, ptr %ptr, i64 102
+    store i64 2, ptr %3, align 8
+    ret void
+  }
+
+  attributes #0 = { minsize }
+
+...
+---
+name:            foo
+alignment:       2
+tracksRegLiveness: true
+liveins:
+  - { reg: '$x10' }
+body:             |
+  bb.0.entry:
+    liveins: $x10
+
+    ; CHECK-LABEL: name: foo
+    ; CHECK: liveins: $x10
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: renamable $x11 = ADDI $x0, 1
+    ; CHECK-NEXT: $x12 = ADDI $x10, 768
+    ; CHECK-NEXT: SD killed renamable $x11, $x12, 32 :: (store (s64) into %ir.1)
+    ; CHECK-NEXT: SD $x12, $x12, 40 :: (store (s64) into %ir.2)
+    ; CHECK-NEXT: renamable $x11 = ADDI $x0, 2
+    ; CHECK-NEXT: SD killed renamable $x11, killed $x12, 48 :: (store (s64) into %ir.3)
+    ; CHECK-NEXT: PseudoRET
+    renamable $x11 = ADDI $x0, 1
+    SD killed renamable $x11, renamable $x10, 800 :: (store (s64) into %ir.1)
+    SD renamable $x10, renamable $x10, 808 :: (store (s64) into %ir.2)
+    renamable $x11 = ADDI $x0, 2
+    SD killed renamable $x11, killed renamable $x10, 816 :: (store (s64) into %ir.3)
+    PseudoRET
+
+...