[llvm] 2247fdc - [SelectionDAG] computeKnownBits / ComputeNumSignBits for the remaining overflow-aware nodes
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 8 01:22:36 PDT 2022
Author: Sergei Barannikov
Date: 2022-07-08T09:19:19+01:00
New Revision: 2247fdc84d74d267b7d82a4103aa60b28065f62a
URL: https://github.com/llvm/llvm-project/commit/2247fdc84d74d267b7d82a4103aa60b28065f62a
DIFF: https://github.com/llvm/llvm-project/commit/2247fdc84d74d267b7d82a4103aa60b28065f62a.diff
LOG: [SelectionDAG] computeKnownBits / ComputeNumSignBits for the remaining overflow-aware nodes
Some overflow-aware nodes were missing from the switches in
computeKnownBits and ComputeNumSignBits.
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/test/CodeGen/AArch64/i256-math.ll
llvm/test/CodeGen/M68k/Control/cmp.ll
llvm/test/CodeGen/M68k/Control/setcc.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 7f381f7b28cb0..dc0bb2e2578d9 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -3271,6 +3271,7 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
Known.Zero.setBitsFrom(1);
break;
case ISD::SETCC:
+ case ISD::SETCCCARRY:
case ISD::STRICT_FSETCC:
case ISD::STRICT_FSETCCS: {
unsigned OpNo = Op->isStrictFPOpcode() ? 1 : 0;
@@ -3506,6 +3507,8 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
break;
case ISD::USUBO:
case ISD::SSUBO:
+ case ISD::SUBCARRY:
+ case ISD::SSUBO_CARRY:
if (Op.getResNo() == 1) {
// If we know the result of a setcc has the top bits zero, use this info.
if (TLI->getBooleanContents(Op.getOperand(0).getValueType()) ==
@@ -3520,6 +3523,10 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
assert(Op.getResNo() == 0 &&
"We only compute knownbits for the
diff erence here.");
+ // TODO: Compute influence of the carry operand.
+ if (Opcode == ISD::SUBCARRY || Opcode == ISD::SSUBO_CARRY)
+ break;
+
Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
Known = KnownBits::computeForAddSub(/* Add */ false, /* NSW */ false,
@@ -3529,6 +3536,7 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
case ISD::UADDO:
case ISD::SADDO:
case ISD::ADDCARRY:
+ case ISD::SADDO_CARRY:
if (Op.getResNo() == 1) {
// If we know the result of a setcc has the top bits zero, use this info.
if (TLI->getBooleanContents(Op.getOperand(0).getValueType()) ==
@@ -3548,7 +3556,7 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
if (Opcode == ISD::ADDE)
// Can't track carry from glue, set carry to unknown.
Carry.resetAll();
- else if (Opcode == ISD::ADDCARRY)
+ else if (Opcode == ISD::ADDCARRY || Opcode == ISD::SADDO_CARRY)
// TODO: Compute known bits for the carry operand. Not sure if it is worth
// the trouble (how often will we find a known carry bit). And I haven't
// tested this very much yet, but something like this might work:
@@ -4108,8 +4116,12 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
return std::min(Tmp, Tmp2);
case ISD::SADDO:
case ISD::UADDO:
+ case ISD::SADDO_CARRY:
+ case ISD::ADDCARRY:
case ISD::SSUBO:
case ISD::USUBO:
+ case ISD::SSUBO_CARRY:
+ case ISD::SUBCARRY:
case ISD::SMULO:
case ISD::UMULO:
if (Op.getResNo() != 1)
@@ -4123,6 +4135,7 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
return VTBits;
break;
case ISD::SETCC:
+ case ISD::SETCCCARRY:
case ISD::STRICT_FSETCC:
case ISD::STRICT_FSETCCS: {
unsigned OpNo = Op->isStrictFPOpcode() ? 1 : 0;
diff --git a/llvm/test/CodeGen/AArch64/i256-math.ll b/llvm/test/CodeGen/AArch64/i256-math.ll
index 9d8ae7b3fc091..232346e7fabe4 100644
--- a/llvm/test/CodeGen/AArch64/i256-math.ll
+++ b/llvm/test/CodeGen/AArch64/i256-math.ll
@@ -98,11 +98,7 @@ define { i256, i8 } @u256_checked_sub(i256 %x, i256 %y) {
; CHECK: // %bb.0:
; CHECK-NEXT: subs x0, x0, x4
; CHECK-NEXT: sbcs x1, x1, x5
-; CHECK-NEXT: cset w8, lo
-; CHECK-NEXT: cmp wzr, w8
; CHECK-NEXT: sbcs x2, x2, x6
-; CHECK-NEXT: cset w8, lo
-; CHECK-NEXT: cmp wzr, w8
; CHECK-NEXT: sbcs x3, x3, x7
; CHECK-NEXT: cset w8, lo
; CHECK-NEXT: eor w4, w8, #0x1
@@ -122,11 +118,7 @@ define { i256, i8 } @u256_overflowing_sub(i256 %x, i256 %y) {
; CHECK: // %bb.0:
; CHECK-NEXT: subs x0, x0, x4
; CHECK-NEXT: sbcs x1, x1, x5
-; CHECK-NEXT: cset w8, lo
-; CHECK-NEXT: cmp wzr, w8
; CHECK-NEXT: sbcs x2, x2, x6
-; CHECK-NEXT: cset w8, lo
-; CHECK-NEXT: cmp wzr, w8
; CHECK-NEXT: sbcs x3, x3, x7
; CHECK-NEXT: cset w4, lo
; CHECK-NEXT: ret
@@ -244,11 +236,7 @@ define { i256, i8 } @i256_checked_sub(i256 %x, i256 %y) {
; CHECK: // %bb.0:
; CHECK-NEXT: subs x0, x0, x4
; CHECK-NEXT: sbcs x1, x1, x5
-; CHECK-NEXT: cset w8, lo
-; CHECK-NEXT: cmp wzr, w8
; CHECK-NEXT: sbcs x2, x2, x6
-; CHECK-NEXT: cset w8, lo
-; CHECK-NEXT: cmp wzr, w8
; CHECK-NEXT: sbcs x3, x3, x7
; CHECK-NEXT: cset w8, vs
; CHECK-NEXT: eor w4, w8, #0x1
@@ -268,11 +256,7 @@ define { i256, i8 } @i256_overflowing_sub(i256 %x, i256 %y) {
; CHECK: // %bb.0:
; CHECK-NEXT: subs x0, x0, x4
; CHECK-NEXT: sbcs x1, x1, x5
-; CHECK-NEXT: cset w8, lo
-; CHECK-NEXT: cmp wzr, w8
; CHECK-NEXT: sbcs x2, x2, x6
-; CHECK-NEXT: cset w8, lo
-; CHECK-NEXT: cmp wzr, w8
; CHECK-NEXT: sbcs x3, x3, x7
; CHECK-NEXT: cset w4, vs
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/M68k/Control/cmp.ll b/llvm/test/CodeGen/M68k/Control/cmp.ll
index db9ee2921f0eb..a5f0b4b542201 100644
--- a/llvm/test/CodeGen/M68k/Control/cmp.ll
+++ b/llvm/test/CodeGen/M68k/Control/cmp.ll
@@ -103,7 +103,6 @@ define i64 @test4(i64 %x) nounwind {
; CHECK-NEXT: subx.l %d0, %d1
; CHECK-NEXT: slt %d1
; CHECK-NEXT: and.l #255, %d1
-; CHECK-NEXT: and.l #1, %d1
; CHECK-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
; CHECK-NEXT: adda.l #4, %sp
; CHECK-NEXT: rts
diff --git a/llvm/test/CodeGen/M68k/Control/setcc.ll b/llvm/test/CodeGen/M68k/Control/setcc.ll
index f18a64d22ac3e..63856e278c9ee 100644
--- a/llvm/test/CodeGen/M68k/Control/setcc.ll
+++ b/llvm/test/CodeGen/M68k/Control/setcc.ll
@@ -46,7 +46,6 @@ define fastcc i64 @t3(i64 %x) nounwind readnone ssp {
; CHECK-NEXT: scs %d0
; CHECK-NEXT: move.l %d0, %d1
; CHECK-NEXT: and.l #255, %d1
-; CHECK-NEXT: and.l #1, %d1
; CHECK-NEXT: lsl.l #6, %d1
; CHECK-NEXT: move.l %d2, %d0
; CHECK-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
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