[llvm] 6c535f9 - [X86][FP16] Fix crash when lowering copysign for f16

[Phoebe Wang via llvm-commits]

Author: Phoebe Wang
Date: 2022-07-07T19:17:26-07:00
New Revision: 6c535f9f1bf8b9516f21353853fc3b6a33c932c6

URL: https://github.com/llvm/llvm-project/commit/6c535f9f1bf8b9516f21353853fc3b6a33c932c6
DIFF: https://github.com/llvm/llvm-project/commit/6c535f9f1bf8b9516f21353853fc3b6a33c932c6.diff

LOG: [X86][FP16] Fix crash when lowering copysign for f16

This is to address the assertion fail reported in https://reviews.llvm.org/D107082#3635612
Not sure if it is a problem of promoting FCOPYSIGN + libcall FP_ROUND.
The promoting will set the rounding mode to 1 https://github.com/llvm/llvm-project/blob/a442c628882eb07fffff8c9f7c87a317af14555a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp#L4810-L4814
While libcall cannot handle the rounding mode equals to 1 https://github.com/llvm/llvm-project/blob/a442c628882eb07fffff8c9f7c87a317af14555a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp#L4324-L4328
So changing the action to Expand to workaround the problem.

Reviewed By: clementval, MaskRay

Differential Revision: https://reviews.llvm.org/D129294

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp
    llvm/test/CodeGen/X86/half.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 7d75423de9c5a..e00d62798c01b 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -594,7 +594,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
     // Half type will be promoted by default.
     setOperationAction(ISD::FABS, MVT::f16, Promote);
     setOperationAction(ISD::FNEG, MVT::f16, Promote);
-    setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote);
+    setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
     setOperationAction(ISD::FADD, MVT::f16, Promote);
     setOperationAction(ISD::FSUB, MVT::f16, Promote);
     setOperationAction(ISD::FMUL, MVT::f16, Promote);

diff  --git a/llvm/test/CodeGen/X86/half.ll b/llvm/test/CodeGen/X86/half.ll
index 1779079df338d..95dc187edcafc 100644
--- a/llvm/test/CodeGen/X86/half.ll
+++ b/llvm/test/CodeGen/X86/half.ll
@@ -1227,6 +1227,41 @@ entry:
   ret void
 }
 
+define half @fcopysign(half %x, half %y) {
+; CHECK-LIBCALL-LABEL: fcopysign:
+; CHECK-LIBCALL:       # %bb.0:
+; CHECK-LIBCALL-NEXT:    pextrw $0, %xmm1, %eax
+; CHECK-LIBCALL-NEXT:    andl $-32768, %eax # imm = 0x8000
+; CHECK-LIBCALL-NEXT:    pextrw $0, %xmm0, %ecx
+; CHECK-LIBCALL-NEXT:    andl $32767, %ecx # imm = 0x7FFF
+; CHECK-LIBCALL-NEXT:    orl %eax, %ecx
+; CHECK-LIBCALL-NEXT:    pinsrw $0, %ecx, %xmm0
+; CHECK-LIBCALL-NEXT:    retq
+;
+; BWON-F16C-LABEL: fcopysign:
+; BWON-F16C:       # %bb.0:
+; BWON-F16C-NEXT:    vpextrw $0, %xmm1, %eax
+; BWON-F16C-NEXT:    andl $-32768, %eax # imm = 0x8000
+; BWON-F16C-NEXT:    vpextrw $0, %xmm0, %ecx
+; BWON-F16C-NEXT:    andl $32767, %ecx # imm = 0x7FFF
+; BWON-F16C-NEXT:    orl %eax, %ecx
+; BWON-F16C-NEXT:    vpinsrw $0, %ecx, %xmm0, %xmm0
+; BWON-F16C-NEXT:    retq
+;
+; CHECK-I686-LABEL: fcopysign:
+; CHECK-I686:       # %bb.0:
+; CHECK-I686-NEXT:    movl $-32768, %eax # imm = 0x8000
+; CHECK-I686-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; CHECK-I686-NEXT:    movzwl {{[0-9]+}}(%esp), %ecx
+; CHECK-I686-NEXT:    andl $32767, %ecx # imm = 0x7FFF
+; CHECK-I686-NEXT:    orl %eax, %ecx
+; CHECK-I686-NEXT:    pinsrw $0, %ecx, %xmm0
+; CHECK-I686-NEXT:    retl
+  %a = call half @llvm.copysign.f16(half %x, half %y)
+  ret half %a
+}
+
 declare half @llvm.fabs.f16(half)
+declare half @llvm.copysign.f16(half, half)
 
 attributes #0 = { nounwind }