[llvm] bbf2725 - [AArch64] Add vector select tests with odd element types.
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 7 14:07:50 PDT 2022
Author: Florian Hahn
Date: 2022-07-07T14:07:25-07:00
New Revision: bbf2725cf6d2b985916219f6f73f61e28cca51d4
URL: https://github.com/llvm/llvm-project/commit/bbf2725cf6d2b985916219f6f73f61e28cca51d4
DIFF: https://github.com/llvm/llvm-project/commit/bbf2725cf6d2b985916219f6f73f61e28cca51d4.diff
LOG: [AArch64] Add vector select tests with odd element types.
Additional tests for D120481.
Added:
Modified:
llvm/test/CodeGen/AArch64/vselect-ext.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/vselect-ext.ll b/llvm/test/CodeGen/AArch64/vselect-ext.ll
index e28d63436e2cb..b3066e5247901 100644
--- a/llvm/test/CodeGen/AArch64/vselect-ext.ll
+++ b/llvm/test/CodeGen/AArch64/vselect-ext.ll
@@ -179,6 +179,30 @@ define <8 x i32> @same_zext_used_in_cmp_unsigned_pred_and_select_v8i32_2(<8 x i1
ret <8 x i32> %sel
}
+
+define <8 x i32> @same_zext_used_in_cmp_unsigned_pred_and_select_v8i32_from_v8i15(<8 x i15> %a) {
+; CHECK-LABEL: same_zext_used_in_cmp_unsigned_pred_and_select_v8i32_from_v8i15:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: movi.8h v1, #10
+; CHECK-NEXT: bic.8h v0, #128, lsl #8
+; CHECK-NEXT: ushll.4s v2, v0, #0
+; CHECK-NEXT: cmhi.8h v1, v0, v1
+; CHECK-NEXT: ushll2.4s v0, v0, #0
+; CHECK-NEXT: ushll2.4s v3, v1, #0
+; CHECK-NEXT: ushll.4s v1, v1, #0
+; CHECK-NEXT: shl.4s v3, v3, #17
+; CHECK-NEXT: shl.4s v1, v1, #17
+; CHECK-NEXT: sshr.4s v3, v3, #17
+; CHECK-NEXT: sshr.4s v4, v1, #17
+; CHECK-NEXT: and.16b v1, v0, v3
+; CHECK-NEXT: and.16b v0, v2, v4
+; CHECK-NEXT: ret
+ %ext = zext <8 x i15> %a to <8 x i32>
+ %cmp = icmp ugt <8 x i15> %a, <i15 10, i15 10, i15 10, i15 10, i15 10, i15 10, i15 10, i15 10>
+ %sel = select <8 x i1> %cmp, <8 x i32> %ext, <8 x i32> zeroinitializer
+ ret <8 x i32> %sel
+}
+
define <7 x i32> @same_zext_used_in_cmp_unsigned_pred_and_select_v7i32(<7 x i16> %a) {
; CHECK-LABEL: same_zext_used_in_cmp_unsigned_pred_and_select_v7i32:
; CHECK: ; %bb.0:
@@ -209,10 +233,10 @@ define <3 x i32> @same_zext_used_in_cmp_unsigned_pred_and_select_v3i16(<3 x i8>
; CHECK: ; %bb.0:
; CHECK-NEXT: fmov s0, w0
; CHECK-NEXT: Lloh0:
-; CHECK-NEXT: adrp x8, lCPI8_0 at PAGE
+; CHECK-NEXT: adrp x8, lCPI9_0 at PAGE
; CHECK-NEXT: mov.h v0[1], w1
; CHECK-NEXT: Lloh1:
-; CHECK-NEXT: ldr d2, [x8, lCPI8_0 at PAGEOFF]
+; CHECK-NEXT: ldr d2, [x8, lCPI9_0 at PAGEOFF]
; CHECK-NEXT: mov.h v0[2], w2
; CHECK-NEXT: fmov d1, d0
; CHECK-NEXT: bic.4h v1, #255, lsl #8
@@ -229,8 +253,6 @@ define <3 x i32> @same_zext_used_in_cmp_unsigned_pred_and_select_v3i16(<3 x i8>
ret <3 x i32> %sel
}
-
-
define <4 x i32> @same_zext_used_in_cmp_unsigned_pred_and_select_v4i32(<4 x i16> %a) {
; CHECK-LABEL: same_zext_used_in_cmp_unsigned_pred_and_select_v4i32:
; CHECK: ; %bb.0:
@@ -279,6 +301,29 @@ define <8 x i32> @same_zext_used_in_cmp_eq_and_select_v8i32(<8 x i16> %a) {
ret <8 x i32> %sel
}
+define <8 x i32> @same_zext_used_in_cmp_eq_and_select_v8i32_from_v8i13(<8 x i13> %a) {
+; CHECK-LABEL: same_zext_used_in_cmp_eq_and_select_v8i32_from_v8i13:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: movi.8h v1, #10
+; CHECK-NEXT: bic.8h v0, #224, lsl #8
+; CHECK-NEXT: ushll.4s v2, v0, #0
+; CHECK-NEXT: cmeq.8h v1, v0, v1
+; CHECK-NEXT: ushll2.4s v0, v0, #0
+; CHECK-NEXT: ushll2.4s v3, v1, #0
+; CHECK-NEXT: ushll.4s v1, v1, #0
+; CHECK-NEXT: shl.4s v3, v3, #19
+; CHECK-NEXT: shl.4s v1, v1, #19
+; CHECK-NEXT: sshr.4s v3, v3, #19
+; CHECK-NEXT: sshr.4s v4, v1, #19
+; CHECK-NEXT: and.16b v1, v0, v3
+; CHECK-NEXT: and.16b v0, v2, v4
+; CHECK-NEXT: ret
+ %ext = zext <8 x i13> %a to <8 x i32>
+ %cmp = icmp eq <8 x i13> %a, <i13 10, i13 10, i13 10, i13 10, i13 10, i13 10, i13 10, i13 10>
+ %sel = select <8 x i1> %cmp, <8 x i32> %ext, <8 x i32> zeroinitializer
+ ret <8 x i32> %sel
+}
+
define <16 x i32> @same_zext_used_in_cmp_ne_and_select_v8i32(<16 x i8> %a) {
; CHECK-LABEL: same_zext_used_in_cmp_ne_and_select_v8i32:
; CHECK: ; %bb.0:
@@ -411,6 +456,34 @@ define <8 x i32> @same_sext_used_in_cmp_eq_and_select_v8i32(<8 x i16> %a) {
ret <8 x i32> %sel
}
+define <8 x i32> @same_sext_used_in_cmp_eq_and_select_v8i32_from_v8i13(<8 x i13> %a) {
+; CHECK-LABEL: same_sext_used_in_cmp_eq_and_select_v8i32_from_v8i13:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: movi.8h v1, #10
+; CHECK-NEXT: mov.16b v2, v0
+; CHECK-NEXT: bic.8h v2, #224, lsl #8
+; CHECK-NEXT: ushll2.4s v3, v0, #0
+; CHECK-NEXT: cmeq.8h v1, v2, v1
+; CHECK-NEXT: ushll.4s v0, v0, #0
+; CHECK-NEXT: ushll.4s v2, v1, #0
+; CHECK-NEXT: ushll2.4s v1, v1, #0
+; CHECK-NEXT: shl.4s v3, v3, #19
+; CHECK-NEXT: shl.4s v1, v1, #19
+; CHECK-NEXT: shl.4s v0, v0, #19
+; CHECK-NEXT: shl.4s v2, v2, #19
+; CHECK-NEXT: sshr.4s v3, v3, #19
+; CHECK-NEXT: sshr.4s v1, v1, #19
+; CHECK-NEXT: sshr.4s v0, v0, #19
+; CHECK-NEXT: sshr.4s v2, v2, #19
+; CHECK-NEXT: and.16b v1, v3, v1
+; CHECK-NEXT: and.16b v0, v0, v2
+; CHECK-NEXT: ret
+ %ext = sext <8 x i13> %a to <8 x i32>
+ %cmp = icmp eq <8 x i13> %a, <i13 10, i13 10, i13 10, i13 10, i13 10, i13 10, i13 10, i13 10>
+ %sel = select <8 x i1> %cmp, <8 x i32> %ext, <8 x i32> zeroinitializer
+ ret <8 x i32> %sel
+}
+
define <16 x i32> @same_sext_used_in_cmp_ne_and_select_v8i32(<16 x i8> %a) {
; CHECK-LABEL: same_sext_used_in_cmp_ne_and_select_v8i32:
; CHECK: ; %bb.0:
@@ -459,6 +532,34 @@ entry:
ret <8 x i32> %sel
}
+define <8 x i32> @same_sext_used_in_cmp_unsigned_pred_and_select_v8i32_from_v8i15(<8 x i15> %a) {
+; CHECK-LABEL: same_sext_used_in_cmp_unsigned_pred_and_select_v8i32_from_v8i15:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: movi.8h v1, #10
+; CHECK-NEXT: shl.8h v2, v0, #1
+; CHECK-NEXT: ushll2.4s v3, v0, #0
+; CHECK-NEXT: sshr.8h v2, v2, #1
+; CHECK-NEXT: ushll.4s v0, v0, #0
+; CHECK-NEXT: shl.4s v3, v3, #17
+; CHECK-NEXT: cmge.8h v1, v2, v1
+; CHECK-NEXT: shl.4s v0, v0, #17
+; CHECK-NEXT: ushll.4s v2, v1, #0
+; CHECK-NEXT: sshr.4s v3, v3, #17
+; CHECK-NEXT: ushll2.4s v1, v1, #0
+; CHECK-NEXT: shl.4s v2, v2, #17
+; CHECK-NEXT: shl.4s v1, v1, #17
+; CHECK-NEXT: sshr.4s v0, v0, #17
+; CHECK-NEXT: sshr.4s v2, v2, #17
+; CHECK-NEXT: sshr.4s v1, v1, #17
+; CHECK-NEXT: and.16b v0, v0, v2
+; CHECK-NEXT: and.16b v1, v3, v1
+; CHECK-NEXT: ret
+ %ext = sext <8 x i15> %a to <8 x i32>
+ %cmp = icmp sge <8 x i15> %a, <i15 10, i15 10, i15 10, i15 10, i15 10, i15 10, i15 10, i15 10>
+ %sel = select <8 x i1> %cmp, <8 x i32> %ext, <8 x i32> zeroinitializer
+ ret <8 x i32> %sel
+}
+
define <16 x i32> @same_sext_used_in_cmp_unsigned_pred_and_select(<16 x i8> %a) {
; CHECK-LABEL: same_sext_used_in_cmp_unsigned_pred_and_select:
; CHECK: ; %bb.0: ; %entry
@@ -522,7 +623,7 @@ define void @extension_in_loop_v16i8_to_v16i32(i8* %src, i32* %dst) {
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: movi.2d v0, #0xffffffffffffffff
; CHECK-NEXT: mov x8, xzr
-; CHECK-NEXT: LBB20_1: ; %loop
+; CHECK-NEXT: LBB24_1: ; %loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr q1, [x0, x8]
; CHECK-NEXT: add x8, x8, #16
@@ -546,7 +647,7 @@ define void @extension_in_loop_v16i8_to_v16i32(i8* %src, i32* %dst) {
; CHECK-NEXT: and.16b v3, v3, v4
; CHECK-NEXT: and.16b v1, v1, v2
; CHECK-NEXT: stp q1, q3, [x1], #64
-; CHECK-NEXT: b.ne LBB20_1
+; CHECK-NEXT: b.ne LBB24_1
; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret
entry:
@@ -575,24 +676,24 @@ define void @extension_in_loop_as_shuffle_v16i8_to_v16i32(i8* %src, i32* %dst) {
; CHECK-LABEL: extension_in_loop_as_shuffle_v16i8_to_v16i32:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: Lloh2:
-; CHECK-NEXT: adrp x9, lCPI21_0 at PAGE
+; CHECK-NEXT: adrp x9, lCPI25_0 at PAGE
; CHECK-NEXT: Lloh3:
-; CHECK-NEXT: adrp x10, lCPI21_1 at PAGE
+; CHECK-NEXT: adrp x10, lCPI25_1 at PAGE
; CHECK-NEXT: Lloh4:
-; CHECK-NEXT: adrp x11, lCPI21_2 at PAGE
+; CHECK-NEXT: adrp x11, lCPI25_2 at PAGE
; CHECK-NEXT: Lloh5:
-; CHECK-NEXT: adrp x12, lCPI21_3 at PAGE
+; CHECK-NEXT: adrp x12, lCPI25_3 at PAGE
; CHECK-NEXT: movi.2d v2, #0xffffffffffffffff
; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: Lloh6:
-; CHECK-NEXT: ldr q0, [x9, lCPI21_0 at PAGEOFF]
+; CHECK-NEXT: ldr q0, [x9, lCPI25_0 at PAGEOFF]
; CHECK-NEXT: Lloh7:
-; CHECK-NEXT: ldr q1, [x10, lCPI21_1 at PAGEOFF]
+; CHECK-NEXT: ldr q1, [x10, lCPI25_1 at PAGEOFF]
; CHECK-NEXT: Lloh8:
-; CHECK-NEXT: ldr q3, [x11, lCPI21_2 at PAGEOFF]
+; CHECK-NEXT: ldr q3, [x11, lCPI25_2 at PAGEOFF]
; CHECK-NEXT: Lloh9:
-; CHECK-NEXT: ldr q4, [x12, lCPI21_3 at PAGEOFF]
-; CHECK-NEXT: LBB21_1: ; %loop
+; CHECK-NEXT: ldr q4, [x12, lCPI25_3 at PAGEOFF]
+; CHECK-NEXT: LBB25_1: ; %loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr q5, [x0, x8]
; CHECK-NEXT: add x8, x8, #16
@@ -614,7 +715,7 @@ define void @extension_in_loop_as_shuffle_v16i8_to_v16i32(i8* %src, i32* %dst) {
; CHECK-NEXT: and.16b v7, v17, v7
; CHECK-NEXT: and.16b v5, v5, v6
; CHECK-NEXT: stp q5, q7, [x1], #64
-; CHECK-NEXT: b.ne LBB21_1
+; CHECK-NEXT: b.ne LBB25_1
; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh5, Lloh9
@@ -648,24 +749,24 @@ define void @shuffle_in_loop_is_no_extend_v16i8_to_v16i32(i8* %src, i32* %dst) {
; CHECK-LABEL: shuffle_in_loop_is_no_extend_v16i8_to_v16i32:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: Lloh10:
-; CHECK-NEXT: adrp x9, lCPI22_0 at PAGE
+; CHECK-NEXT: adrp x9, lCPI26_0 at PAGE
; CHECK-NEXT: Lloh11:
-; CHECK-NEXT: adrp x10, lCPI22_1 at PAGE
+; CHECK-NEXT: adrp x10, lCPI26_1 at PAGE
; CHECK-NEXT: Lloh12:
-; CHECK-NEXT: adrp x11, lCPI22_2 at PAGE
+; CHECK-NEXT: adrp x11, lCPI26_2 at PAGE
; CHECK-NEXT: Lloh13:
-; CHECK-NEXT: adrp x12, lCPI22_3 at PAGE
+; CHECK-NEXT: adrp x12, lCPI26_3 at PAGE
; CHECK-NEXT: movi.2d v2, #0xffffffffffffffff
; CHECK-NEXT: mov x8, xzr
; CHECK-NEXT: Lloh14:
-; CHECK-NEXT: ldr q0, [x9, lCPI22_0 at PAGEOFF]
+; CHECK-NEXT: ldr q0, [x9, lCPI26_0 at PAGEOFF]
; CHECK-NEXT: Lloh15:
-; CHECK-NEXT: ldr q1, [x10, lCPI22_1 at PAGEOFF]
+; CHECK-NEXT: ldr q1, [x10, lCPI26_1 at PAGEOFF]
; CHECK-NEXT: Lloh16:
-; CHECK-NEXT: ldr q3, [x11, lCPI22_2 at PAGEOFF]
+; CHECK-NEXT: ldr q3, [x11, lCPI26_2 at PAGEOFF]
; CHECK-NEXT: Lloh17:
-; CHECK-NEXT: ldr q4, [x12, lCPI22_3 at PAGEOFF]
-; CHECK-NEXT: LBB22_1: ; %loop
+; CHECK-NEXT: ldr q4, [x12, lCPI26_3 at PAGEOFF]
+; CHECK-NEXT: LBB26_1: ; %loop
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr q5, [x0, x8]
; CHECK-NEXT: add x8, x8, #16
@@ -687,7 +788,7 @@ define void @shuffle_in_loop_is_no_extend_v16i8_to_v16i32(i8* %src, i32* %dst) {
; CHECK-NEXT: and.16b v7, v17, v7
; CHECK-NEXT: and.16b v5, v5, v6
; CHECK-NEXT: stp q5, q7, [x1], #64
-; CHECK-NEXT: b.ne LBB22_1
+; CHECK-NEXT: b.ne LBB26_1
; CHECK-NEXT: ; %bb.2: ; %exit
; CHECK-NEXT: ret
; CHECK-NEXT: .loh AdrpLdr Lloh13, Lloh17
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