[PATCH] D129282: [AArch64][SVE] Ensure PTEST operands have type nxv16i1

[Rosie Sumpter via Phabricator via llvm-commits]

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Currently any legal predicate types will be pattern-matched when
creating a PTEST instruction. This could be a problem in future since
PTEST always uses the .B specifier for the operand, but it is not
always guaranteed that the extra lanes of unpacked types (e.g. nxv4i1)
are zero. This patch ensures the operands of PTEST are type nxv16i1,
where the undef lanes are set to zero.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D129282

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/sve-setcc.ll

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