[PATCH] D129281: [llvm][SVE] Remove redundant and when comparing against extending load

[David Truby via Phabricator via llvm-commits]

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When determining if an `and` should be merged into an extending load
the constant argument to the `and` is currently not checked if the
argument requires truncation. This prevents the combine happening when
the vector width is half the normal available vector width for SVE VLA
vectors.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D129281

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/sve-extload-icmp.ll

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