[PATCH] D128631: [AArch64] Initial sched model for Neoverse N2

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes updated this revision to Diff 442826.
c-rhodes added a comment.

The one reg variant of EXTR (both input registers are the same, can’t be modelled) was incorrectly modelled as the W form. Use the two regs properties for W form.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128631/new/

https://reviews.llvm.org/D128631

Files:
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64SchedA53.td
  llvm/lib/Target/AArch64/AArch64SchedA55.td
  llvm/lib/Target/AArch64/AArch64SchedA57.td
  llvm/lib/Target/AArch64/AArch64SchedA64FX.td
  llvm/lib/Target/AArch64/AArch64SchedAmpere1.td
  llvm/lib/Target/AArch64/AArch64SchedCyclone.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
  llvm/lib/Target/AArch64/AArch64SchedFalkor.td
  llvm/lib/Target/AArch64/AArch64SchedKryo.td
  llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
  llvm/lib/Target/AArch64/AArch64SchedTSV110.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
  llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s
  llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-mte-instructions.s
  llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-neon-instructions.s
  llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-sve-instructions.s