[PATCH] D128631: [AArch64] Initial sched model for Neoverse N2

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Thanks for the cleanup and second patch. I think apart from the EXTR question this looks good.



================
Comment at: llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s:1858
+# CHECK-NEXT:  1      2     0.50                        umnegl	x11, w13, w17
+# CHECK-NEXT:  1      1     0.25                        extr	w3, w5, w7, #0
+# CHECK-NEXT:  1      1     0.25                        extr	w11, w13, w17, #31
----------------
c-rhodes wrote:
> dmgreen wrote:
> > Is this missing?
> > Is this missing?
> 
> I can't see any issue with this?
I meant should it be the same as `extr x`? The software optimization guide mentions "Bitfield extract, one reg" and "Bitfield extract, two regs", but doesn't make a distinction between X regs and W.

We don't model the difference between EXTR where both operands are the same (if that's what "one reg" means) - that should be fine as it sounds minor. But should the matching be including W EXT too:
```
def : InstRW<[N2Write_3cyc_1I_1M], (instrs EXTRXrri, EXTRWrri)>;
```


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