[PATCH] D129207: [X86] isTargetShuffleEquivalent - attempt to match SM_SentinelZero shuffle mask elements using known bits

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: craig.topper, pengfei, spatel.
Herald added subscribers: jsji, StephenFan, hiraditya.
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RKSimon requested review of this revision.
Herald added a project: LLVM.

If the combined shuffle mask contains required zero elements, we don't currently have much chance of matching them against the expected source vector. This patch uses the SelectionDAG::MaskedVectorIsZero wrapper to attempt to determine if the element we want to use is already known to be zero.

Given how expensive known bits can be I've limited this to avoid speculative matching of zero elements - I originally had a more complicated version that only attempted to match zero elements if all other elements were already matched - I can reattempt that variant if people think the known bits call costs is still too high.

This attempts to address some of the regressions uncovered by D129150 <https://reviews.llvm.org/D129150> where we more aggressively fold shuffles as AND / 'clear' masks which results in more combined shuffles using SM_SentinelZero.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D129207

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/pr51615.ll
  llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
  llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
  llvm/test/CodeGen/X86/vector-shuffle-combining.ll
  llvm/test/CodeGen/X86/vector_splat-const-shift-of-constmasked.ll

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