[PATCH] D129201: [MachineVerifier] Try harder to verify SlotIndexes

[Jay Foad via Phabricator via llvm-commits]

foad created this revision.
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Verify the SlotIndexes analysis after a pass that claims to preserve it,
even if there are no further passes (apart from the verifier itself)
that would use the analysis.

FIXME: CodeGen/AMDGPU/si-lower-control-flow.mir fails with:

- Bad machine code: Instruction index out of order ***

perhaps because SILowerControlFlow::emitEndCf misuses
LiveIntervals::handleMove to handle an instruction that has moved into a
different basic block.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D129201

Files:
  llvm/lib/CodeGen/MachineVerifier.cpp


Index: llvm/lib/CodeGen/MachineVerifier.cpp
===================================================================
--- llvm/lib/CodeGen/MachineVerifier.cpp
+++ llvm/lib/CodeGen/MachineVerifier.cpp
@@ -293,6 +293,7 @@
       }
 
     void getAnalysisUsage(AnalysisUsage &AU) const override {
+      AU.addUsedIfAvailable<SlotIndexes>();
       AU.setPreservesAll();
       MachineFunctionPass::getAnalysisUsage(AU);
     }


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