[PATCH] D128996: [LegalizeTypes] Replace vecreduce_xor/or/and with vecreduce_add/umax/umin if not legal

Tue Jul 5 17:02:00 PDT 2022

paulwalker-arm accepted this revision.
paulwalker-arm added a comment.
This revision is now accepted and ready to land.

Looks good to me but with a couple of observations.

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Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:2273
+  // vecreduce_or is not legal
+  if (Opcode == ISD::VECREDUCE_OR && OrigEltVT == MVT::i1 &&
+      !TLI.isOperationLegalOrCustom(ISD::VECREDUCE_OR, InVT) &&
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Perhaps this should be `else if`? Same goes for the next if block.

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Comment at: llvm/test/CodeGen/AArch64/reduce-and.ll:169-171
+define <16 x i1> @test_redand_ins_v16i1(<16 x i1> %a) {
+; CHECK-LABEL: test_redand_ins_v16i1:
+; CHECK:       // %bb.0:
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Are the `_ins_` tests strictly necessary? It's not immediately obvious how they relate to your code changes.

Repository:
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https://reviews.llvm.org/D128996