[PATCH] D129095: [AMDGPU][CodeGen] Match complex register SMRD offsets.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/amdgcn-load-offset-from-reg.ll:1-2
-; Test that DAG->DAG ISel is able to pick up the S_LOAD_DWORDX4_SGPR instruction that fetches the offset
-; from a register.
-
-; RUN: llc -march=amdgcn -verify-machineinstrs -stop-after=amdgpu-isel -o - %s | FileCheck -check-prefix=GCN %s
-; RUN: llc -march=amdgcn -global-isel -verify-machineinstrs -stop-after=amdgpu-isel -o - %s | FileCheck -check-prefix=GISEL %s
+; RUN: llc -march=amdgcn -verify-machineinstrs -stop-after=amdgpu-isel -o - %s | FileCheck -check-prefixes=GCN,SDAG %s
+; RUN: llc -march=amdgcn -global-isel -verify-machineinstrs -stop-after=amdgpu-isel -o - %s | FileCheck -check-prefixes=GCN,GISEL %s
 
----------------
Should use explicit global-isel=0 for dag test


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Comment at: llvm/test/CodeGen/AMDGPU/amdgcn-load-offset-from-reg.ll:34-35
+; GCN-LABEL: name: test_complex_reg_offset
+; CCN: S_LOAD_DWORD_IMM
+; GCN: S_LOAD_DWORD_SGPR
+define amdgpu_ps void @test_complex_reg_offset(float addrspace(1)* %out) {
----------------
Should test the operands


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Comment at: llvm/test/CodeGen/AMDGPU/amdgcn-load-offset-from-reg.ll:45
+}
+
 declare void @llvm.amdgcn.raw.buffer.store.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32 immarg) #1
----------------
Doesn't test the 32-bit constant case


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129095/new/

https://reviews.llvm.org/D129095