[PATCH] D129095: [AMDGPU][CodeGen] Match complex register SMRD offsets.

[Ivan Kosarev via Phabricator via llvm-commits]

kosarev marked 2 inline comments as done.
kosarev added inline comments.


================
Comment at: llvm/test/CodeGen/AMDGPU/amdgcn-load-offset-from-reg.ll:33
+; GCN: S_LOAD_DWORD_SGPR
+define amdgpu_ps void @test_complex_reg_offset(float addrspace(1)* %out) {
+  %i = load i32, i32 addrspace(4)* @1
----------------
foad wrote:
> When this patch and D128836 have both landed, can you add GISEL checks here please.
Done; the GCN checks now work for both the SDAG and GISEL runs.


================
Comment at: llvm/test/CodeGen/AMDGPU/amdgcn-load-offset-from-reg.ll:37
+  %2 = zext i32 %1 to i64
+  %3 = getelementptr [4 x <2 x float>], [4 x <2 x float>] addrspace(4)* @0, i64 0, i64 %2, i64 0
+  %4 = load float, float addrspace(4)* %3, align 4
----------------
foad wrote:
> Do I understand correctly: in SDag this gep ends up as `(add %2, @0) ` (not `(add @0, %2)`) because `@0` is a constant so it gets canonicalized to the RHS?
That's right, for commutative nodes the combiner tries to make whatever seems a constant be the second operand.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129095/new/

https://reviews.llvm.org/D129095