[PATCH] D129106: [RISCV] Add support for static chain

[Luís Marques via Phabricator via llvm-commits]

luismarques added a comment.

I guess this patch should update the other conventions as well? E.g. error out if nest is used with the GHC CC. There's also the FastCC.



================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:10206-10207
 
+  // Static chain parameter must not be passed in normal argument registers,
+  // so we assign t2 for it as did in GCC's __builtin_call_with_static_chain
+  if (ArgFlags.isNest()) {
----------------
Nit: "as did" -> "as done"


================
Comment at: llvm/test/CodeGen/RISCV/nest-register.ll:1-9
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32I %s
+; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32IM %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64I %s
----------------
Checking RV32IM and RV64IM is not needed.


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  https://reviews.llvm.org/D129106/new/

https://reviews.llvm.org/D129106