[PATCH] D129095: [AMDGPU][CodeGen] Match complex register SMRD offsets.

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/amdgcn-load-offset-from-reg.ll:33
+; GCN: S_LOAD_DWORD_SGPR
+define amdgpu_ps void @test_complex_reg_offset(float addrspace(1)* %out) {
+  %i = load i32, i32 addrspace(4)* @1
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When this patch and D128836 have both landed, can you add GISEL checks here please.


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Comment at: llvm/test/CodeGen/AMDGPU/amdgcn-load-offset-from-reg.ll:35
+  %i = load i32, i32 addrspace(4)* @1
+  %1 = and i32 %i, 3
+  %2 = zext i32 %1 to i64
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Please don't use unnamed values in tests. (You can run the IR through `opt -instnamer` to name them automatically.)


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Comment at: llvm/test/CodeGen/AMDGPU/amdgcn-load-offset-from-reg.ll:37
+  %2 = zext i32 %1 to i64
+  %3 = getelementptr [4 x <2 x float>], [4 x <2 x float>] addrspace(4)* @0, i64 0, i64 %2, i64 0
+  %4 = load float, float addrspace(4)* %3, align 4
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Do I understand correctly: in SDag this gep ends up as `(add %2, @0) ` (not `(add @0, %2)`) because `@0` is a constant so it gets canonicalized to the RHS?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129095/new/

https://reviews.llvm.org/D129095