[PATCH] D129106: [RISCV] Add support for static chain

[Funan Zeng via Phabricator via llvm-commits]

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The static chain parameter is a special parameter that is not passed in the usual argument registers or stack space. For example, in x64 System V ABI it is always passed in R10 <https://reviews.llvm.org/source/svn-test-suite/>. Although the ABI of RISCV does not assign a register for this purpose, GCC had support for it on RISC-V a long time ago, and it is exposed via `__builtin_call_with_static_chain` intrinsic, and assign t2 for static chain parameters. This patch also chose t2 for compatibility.

In LLVM, static chain parameters are handled by the `nest` attribute of an argument to a function (D6332 <https://reviews.llvm.org/D6332>), so tests are added to ensure `nest` arguments are handled correctly.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D129106

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/nest-register.ll

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