[llvm] f276729 - [RISCV] Replace an explicit check with an assert.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-07-04T23:21:54-07:00
New Revision: f27672924e369fc4c6a2f0fe31502e5a1a2ec593

URL: https://github.com/llvm/llvm-project/commit/f27672924e369fc4c6a2f0fe31502e5a1a2ec593
DIFF: https://github.com/llvm/llvm-project/commit/f27672924e369fc4c6a2f0fe31502e5a1a2ec593.diff

LOG: [RISCV] Replace an explicit check with an assert.

Shift amounts should never be 0 or more than bitwidth - 1.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index c4043b66b8f0..334ee496e746 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -854,10 +854,9 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
     auto *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
     if (!C)
       break;
-    uint64_t C2 = C->getZExtValue();
+    unsigned C2 = C->getZExtValue();
     unsigned XLen = Subtarget->getXLen();
-    if (!C2 || C2 >= XLen)
-      break;
+    assert((C2 > 0 && C2 < XLen) && "Unexpected shift amount!");
 
     uint64_t C1 = N1C->getZExtValue();