[llvm] 063500a - [RISCV][NFC] Merge the isolated decleration into foreach.

[via llvm-commits]

Author: jacquesguan
Date: 2022-07-05T10:17:45+08:00
New Revision: 063500afc0b80ac034a26fa9cb5b978cd7293bc6

URL: https://github.com/llvm/llvm-project/commit/063500afc0b80ac034a26fa9cb5b978cd7293bc6
DIFF: https://github.com/llvm/llvm-project/commit/063500afc0b80ac034a26fa9cb5b978cd7293bc6.diff

LOG: [RISCV][NFC] Merge the isolated decleration into foreach.

Reviewed By: benshi001

Differential Revision: https://reviews.llvm.org/D129063

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoV.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index f8bc241039f89..d466e278cafce 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -1476,14 +1476,9 @@ defm VCOMPRESS_V : VCPR_MV_Mask<"vcompress", 0b010111>;
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
     RVVConstraint = NoConstraint in {
-def VMV1R_V  : RVInstV<0b100111, 0, OPIVI, (outs VR:$vd), (ins VR:$vs2),
-                       "vmv1r.v", "$vd, $vs2">, VMVRSched<1> {
-  let Uses = [];
-  let vm = 1;
-}
 // A future extension may relax the vector register alignment restrictions.
-foreach n = [2, 4, 8] in {
-  defvar vrc = !cast<VReg>("VRM"#n);
+foreach n = [1, 2, 4, 8] in {
+  defvar vrc = !cast<VReg>(!if(!eq(n, 1), "VR", "VRM"#n));
   def VMV#n#R_V  : RVInstV<0b100111, !add(n, -1), OPIVI, (outs vrc:$vd),
                            (ins vrc:$vs2), "vmv" # n # "r.v", "$vd, $vs2">,
                    VMVRSched<n> {