[PATCH] D129083: [AArch64][SME] Update load/store intrinsics to take predicate corresponding to element size.

[Sander de Smalen via Phabricator via llvm-commits]

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Instead of using <vscale x 16 x i1> for all the loads/stores, we now use the appropriate
predicate type according to the element size, e.g.

  ld1b uses <vscale x 16 x i1>
  ld1w uses <vscale x 4 x i1>
  ld1q uses <vscale x 1 x i1>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D129083

Files:
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/test/CodeGen/AArch64/sme-intrinsics-loads.ll
  llvm/test/CodeGen/AArch64/sme-intrinsics-stores.ll

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