[PATCH] D129081: [AArch64][SVE] Zero other lanes when doing OR reduction on unpacked predicate using ptest.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen created this revision.
sdesmalen added reviewers: paulwalker-arm, efriedma, RosieSumpter.
Herald added subscribers: psnobl, hiraditya, kristof.beyls, tschuett.
Herald added a project: All.
sdesmalen requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

When the predicate vector is unpacked, we cannot assume anything about the
values in the other lanes. We have to make sure we use the correct
predicate where we know that the other lanes have been zeroed.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D129081

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-int-pred-reduce.ll
  llvm/test/CodeGen/AArch64/sve-vecreduce-fold.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D129081.442096.patch
Type: text/x-patch
Size: 5173 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220704/e7c2ae40/attachment.bin>