[PATCH] D128975: [AArc64] Add support for insert/extract for nxv1i1 types.

[David Sherwood via Phabricator via llvm-commits]

david-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:1541
             (PUNPKHI_PP (PUNPKHI_PP PPR:$Ps))>;
-
   def : Pat<(nxv4i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 0))),
----------------
nit: whitespace change


================
Comment at: llvm/test/CodeGen/AArch64/sve-insert-vector.ll:711
 
+;
+; Insert nxv1i1 type into: nxv2i1
----------------
Is there value in adding a simple test that inserts <vscale x 1 x i1> into a <vscale x 1 x i1> vector? I assume that standard DAG combines will treat this as a simple copy?


================
Comment at: llvm/test/CodeGen/AArch64/sve-insert-vector.ll:992
+; CHECK-NEXT:    punpklo p2.h, p0.b
+; CHECK-NEXT:    str p4, [sp, #7, mul vl] // 2-byte Folded Spill
+; CHECK-NEXT:    punpklo p3.h, p2.b
----------------
I don't think this is a problem with your patch, but the spill and fill in this output looks unnecessary. We have enough registers to support this without spilling I think?

Also, something weird seems to be happening with the offset for the spill/fill, i.e. "#7, mul vl". I assume that translates to offset = 7 x vscale x 2? It seems to fit into the stack space we've allocated, but I wonder if this is just pure luck?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128975/new/

https://reviews.llvm.org/D128975